L1_TM_ANA_BYP_15 (SERDES) Register Description
| Register Name | L1_TM_ANA_BYP_15 |
|---|---|
| Offset Address | 0x0000005038 |
| Absolute Address | 0x00FD405038 (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L1_TM_ANA_BYP_15 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_ANA_BYP_15_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| uphy_ENABLE_LOW_LEAKAGE | 7 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_uphy_ENABLE_LOW_LEAKAGE | 6 | rwNormal read/write | 0x0 | Value generated by PCW. |
| uphy_PD_SAMP_C2C | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_uphy_PD_SAMP_C2C | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| uphy_PSO_CORE_EQ | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_uphy_PSO_CORE_EQ | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| uphy_PSO_IO_EQ | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_uphy_PSO_IO_EQ | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |