PS_CTRL_STATUS (AMS) Register Description
| Register Name | PS_CTRL_STATUS |
|---|---|
| Offset Address | 0x0000000040 |
| Absolute Address | 0x00FFA50040 (AMS_CTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | PS SysMon Unit Control and Status |
PS_CTRL_STATUS (AMS) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:28 | roRead-only | 0x0 | reserved |
| startup_state | 27:24 | roRead-only | 0x0 | Reserved. State of the Configuration sequence, refer to the [startup_trigger] bit for more information. 0: Pre-trim settle. 1: Wait. 2: Memory cell reset. 3: Wait for eFuse readout and oscillator to settle. 4: Pre-configuration wait. 5: Memory cell initialization. 6: Post-configuration wait. 7: Wait for MON_STAT.jtag_locked = 0. 8: Idle (PS SysMon is Ready) 9: reserved 10: Prepare for scan mode 11: Scan mode sequence Others: reserved |
| Reserved | 23:17 | roRead-only | 0x0 | reserved |
| startup_done | 16 | roRead-only | 0x0 | Reserved. Global config sequence completed, refer to the [startup_trigger] bit for more information. |
| Reserved | 15:4 | roRead-only | 0x0 | reserved |
| auto_convst | 3 | rwNormal read/write | 0x0 | Enable a sequence of measurements. 0: One conversion (EOC). 1: Sequence of conversions (EOS). When enabled, the PS SysMon unit will loop through once and set EOS if averaging is off. If averaging is on, the PS SysMon unit will loop through the number times defined for averaging. |
| convst | 2 | woWrite-only | 0x0 | Trigger start-of-conversion. Write-only. 0: no effect. 1: trigger conversion. This bit self-clears. This mechanism is similar to the event trigger in the PL SysMon unit. |
| reset_user | 1 | rwNormal read/write | 0x0 | Reset for the PS SysMon. 0: no reset. 1: reset asserted. Write a 1 than a 0 to reset and release the PS system monitor. |
| startup_trigger | 0 | rwNormal read/write | 0x0 | Trigger PS Sysmon configuration sequence, if needed for test/debug. READ: 0: done. 1: in-process. WRITE: 0: no effect. 1: initiate the configuration sequence. When the process is done, the hardware clears this bit to 0. Note: this is similar to the automatic configuration routine run in the PL SysMon after a power-up cycle. |