PxDEVSLP (SATA_AHCI_PORTCNTRL) Register Description
| Register Name | PxDEVSLP |
|---|---|
| Offset Address | 0x0000000044 |
| Absolute Address |
0x00FD0C0144 (SATA_AHCI_PORT0_CNTRL) 0x00FD0C01C4 (SATA_AHCI_PORT1_CNTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000002 |
| Description | PxDEVSLP - Port x Device Sleep |
PxDEVSLP (SATA_AHCI_PORTCNTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:29 | roRead-only | 0x0 | Reserved |
| DM | 28:25 | roRead-only | 0x0 | DITO Multiplier (DM): 0s based value that specifies the DITO multiplier that the HBA applies to the specified DITO value, effectively extending the range of DITO from 1ms to 16368ms. A value of 0h indicates a multiplier of 1. A maximum multiplier of 16 may be applied. The HBA computes the total idle timeout as a product of DM and DITO (i.e. DITOactual = DITO * (DM+1)). |
| DITO | 24:15 | rwNormal read/write | 0x0 | Device Sleep Idle Timeout (DITO): This field specifies the amount of the time (in approximate 1ms granularity) that the HBA shall wait before driving the DEVSLP signal. Refer to section 8.5.1.1.1 for details. Hardware reloads its port specific Device Sleep timer with this value each time the port transitions out of the DEVSLP state. For example: from DevSleep to active or PxDEVSLP.ADSE transitions from 0 to a 1. If CAP2.SDS is cleared to 0 or CAP2.SADM is cleared to 0 or PxDEVSLP.DSP is cleared to 0 then these bits are read-only 0h and software shall treat these bits as reserved. If CAP2.SDS is set to 1 and CAP2.SADM is set to 1 and PxDEVSLP.DSP is set to 1 then these bits are read-write. Software shall only set this value when PxCMD.ST is cleared to 0 and PxDEVSLP.ADSE is cleared to 0. |
| MDAT | 14:10 | rwNormal read/write | 0x0 | Minimum Device Sleep Assertion Time (MDAT): This field specifies the minimum amount of time (in 1ms granularity) that the HBA must assert the DEVSLP signal before it may be de-asserted. The nominal value is 10ms and the minimum is 1ms depending on device identification information. If CAP2.SDS is cleared to 0 or PxDEVSLP.DSP is cleared to 0 then these bits are read-only 0h and software shall treat these bits as reserved. If CAP2.SDS is set to 1 and PxDEVSLP.DSP is set to 1 then these bits are read-write. Software shall only set this value when PxCMD.ST is cleared to 0, PxDEVSLP.ADSE is cleared to 0, and prior to setting PxCMD.ICC to 8h. |
| DETO | 9:2 | rwNormal read/write | 0x0 | Device Sleep Exit Timeout (DETO): This field specifies the maximum duration (in approximate 1ms granularity) from DEVSLP de-assertion until the device is ready to accept OOB. The nominal value is 20ms while the max value is 255ms depending on device identification information. If CAP2.SDS is cleared to 0 or PxDEVSLP.DSP is cleared to 0 then these bits are read-only 0h and software shall treat these bits as reserved. If CAP2.SDS is set to 1 and PxDEVSLP.DSP is set to 1 then these bits are read-write. Software shall only set this value when PxCMD.ST is cleared to 0, PxDEVSLP.ADSE is cleared to 0, and prior to setting PxCMD.ICC to 8h. |
| DSP | 1 | roRead-only | 0x1 | Device Sleep Present (DSP): If set to 1, the platform supports Device Sleep on this port. If cleared to 0, the platform does not support Device Sleep on this port. This bit may only be set to 1 if CAP2.SDS is set to 1. DSP is mutually exclusive with the PxCMD.HPCP bit and PxCMD.ESP bit. |
| ADSE | 0 | rwNormal read/write | 0x0 | Aggressive Device Sleep Enable (ADSE): When this bit is set to 1, the HBA shall assert the DEVSLP signal after the port has been idle (PxCI = 0h and PxSACT = 0h) for the amount of time specified by the PxDEVSLP.DITO register. When this bit is set to 1 and CAP2.DESO is set to 1, the HBA shall assert the DEVSLP signal after the port has been idle (PxCI = 0h and PxSACT = 0h) for the amount of time specified by PxDEVSLP.DITO and the interface is in Slumber (PxSSTS.IPM = 6h).When this bit is cleared to 0, the HBA does not enter DevSleep unless software directed via PxCMD.ICC. This bit shall only be set to 1 if PxDEVSLP.DSP is set to 1. If CAP2.SDS is cleared to 0 or CAP2.SADM is cleared to 0 or if PxDEVSLP.DSP is cleared to 0, then these bits are read-only 0h and software shall treat these bits as reserved. If CAP2.SDS is set to 1 and CAP2.SADM is set to 1 and if PxDEVSLP.DSP is set to 1, then these bits are read-write. |