VCU_ISR (VCU_SLCR) Register Description
| Register Name | VCU_ISR |
|---|---|
| Offset Address | 0x0000000070 |
| Absolute Address | 0x00A0040070 (VCU_SLCR) |
| Width | 32 |
| Type | wtcReadable, write a 1 to clear |
| Reset Value | 0x00000000 |
| Description | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
VCU_ISR (VCU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| apm3_fifo3_ovfl | 19 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 2nd read latency measurement FIFO. This is for second Decoder AXI4 Bus. |
| apm3_fifo2_ovfl | 18 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 1st read latency measurement FIFO. This is for second Decoder AXI4 Bus. |
| apm3_fifo1_ovfl | 17 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 2nd write latency measurement FIFO. This is for second Decoder AXI4 Bus. |
| apm3_fifo0_ovfl | 16 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 1st write latency measurement FIFO. This is for second Decoder AXI4 Bus. |
| apm3_result_valid | 15 | wtcReadable, write a 1 to clear | 0x0 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for second Decoder AXI4 Bus. |
| apm2_fifo3_ovfl | 14 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 2nd read latency measurement FIFO. This is for first Decoder AXI4 Bus. |
| apm2_fifo2_ovfl | 13 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 1st read latency measurement FIFO. This is for first Decoder AXI4 Bus. |
| apm2_fifo1_ovfl | 12 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 2nd write latency measurement FIFO. This is for first Decoder AXI4 Bus. |
| apm2_fifo0_ovfl | 11 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 1st write latency measurement FIFO. This is for first Decoder AXI4 Bus. |
| apm2_result_valid | 10 | wtcReadable, write a 1 to clear | 0x0 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for first Decoder AXI4 Bus. |
| apm1_fifo3_ovfl | 9 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 2nd read latency measurement FIFO. This for is second Encoder AXI4 Bus. |
| apm1_fifo2_ovfl | 8 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 1st read latency measurement FIFO. This is for second Encoder AXI4 Bus. |
| apm1_fifo1_ovfl | 7 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 2nd write latency measurement FIFO. This is for second Encoder AXI4 Bus. |
| apm1_fifo0_ovfl | 6 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 1st write latency measurement FIFO. This is for second Encoder AXI4 Bus. |
| apm1_result_valid | 5 | wtcReadable, write a 1 to clear | 0x0 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for second Encoder AXI4 Bus. |
| apm0_fifo3_ovfl | 4 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 2nd read latency measurement FIFO. This is for first Encoder AXI4 Bus. |
| apm0_fifo2_ovfl | 3 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 1st read latency measurement FIFO. This is for first Encoder AXI4 Bus. |
| apm0_fifo1_ovfl | 2 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 2nd write latency measurement FIFO. This is for first Encoder AXI4 Bus. |
| apm0_fifo0_ovfl | 1 | wtcReadable, write a 1 to clear | 0x0 | Overflow occured on 1st write latency measurement FIFO. This is for first Encoder AXI4 Bus. |
| apm0_result_valid | 0 | wtcReadable, write a 1 to clear | 0x0 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is first Encoder AXI4 Bus. |