SWSTAT (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SWSTAT (DDRC) Register Description

Register NameSWSTAT
Offset Address0x0000000324
Absolute Address 0x00FD070324 (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionSoftware register programming control status

SWSTAT (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
sw_done_ack 0roRead-only0x0Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains.