QSPIDMA_DST_ADDR_MSB (QSPI) Register Description
Register Name | QSPIDMA_DST_ADDR_MSB |
---|---|
Offset Address | 0x0000000828 |
Absolute Address | 0x00FF0F0828 (QSPI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | DMA destination memory address (MSBs) |
For DMA stream-to-memory data transfer.
QSPIDMA_DST_ADDR_MSB (QSPI) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:12 | razRead as zero | 0x0 | reserved |
ADDR_MSB | 11:0 | woWrite-only | 0x0 | DMA destination memory address (msbs) for stream to memory data transfer. Refer to the description for [QSPIDMA_DST_ADDR]. This field is the 12 msbs of the full 44-bit DST address. MSBs for 44-bit DMA Destination Address. The address is comprised of three fields: [ADDR_MSB] with 12 MSBs. QSPIDMA_DST_ADDR [ADDR] with 30 bits. 00 of two LSBs. Note: Change this value only when controller is not processing commands. |