QSPIDMA_DST_CTRL2 (QSPI) Register Description
| Register Name | QSPIDMA_DST_CTRL2 |
|---|---|
| Offset Address | 0x0000000824 |
| Absolute Address | 0x00FF0F0824 (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x0000FFF8 |
| Description | General DST DMA Control Reg 2 |
QSPIDMA_DST_CTRL2 (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:28 | razRead as zero | 0x0 | reserved |
| AWCACHE | 26:24 | rwNormal read/write | 0x0 | Controls the AWCACHE bits of the AXI Write transaction: Bit[24]: AXI AwCache[0] signal. Bit[25]: AXI AwCache[2] signal. Bit[26]: AXI AwCache[3] signal. Note: AXI AwCache[1] signal is always driven to 1. Note: Change this value only when controller is not processing commands. |
| Reserved | 23 | razRead as zero | 0x0 | reserved |
| TIMEOUT_EN | 22 | rwNormal read/write | 0x0 | Timeout Counters 1 and 2 common enable: 0: disable. 1: enable. Note: Change this value only when controller is not processing commands. |
| TIMEOUT_PRE | 15:4 | rwNormal read/write | 0xFFF | Set the prescaler value for the timeout in clk (~2.5ns) cycles (Refer to [TIMEOUT_VAL] description). The [TIMEOUT_PRE] field is interpreted as follows: 000: Prescaler enables timer every cycle. 001: Prescaler enables timer every 2 cycles. .. FFF: Prescaler enables timer every 4096 cycles. Note: Change this value only when controller is not processing commands. |
| MAX_OUTS_CMDS | 3:0 | rwNormal read/write | 0x8 | Controls the maximum number of outstanding AXI write commands issued. The field is interpreted as follows: 0: Max of 1 Outstanding Write command allowed 1 to 8: Max of 2 to 9 Outstanding Write commands allowed Note: Change this value only when controller is not processing commands. |