GP_CONTR_REG_WATCHDOG_DISABLE (GPU) Register Description
| Register Name | GP_CONTR_REG_WATCHDOG_DISABLE |
|---|---|
| Offset Address | 0x00000000A0 |
| Absolute Address | 0x00FD4B00A0 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | GP Control Register Watchdog Disable |
GP_CONTR_REG_WATCHDOG_DISABLE (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | rwNormal read/write | 0x0 | Reserved, read as zero |
| GP_CONTR_REG_WATCHDOG_DISABLE | 0 | rwNormal read/write | 0x0 | Disable watchdog timer |