PP1_WB1_TARGET_PIXEL_FORMAT (GPU) Register Description
| Register Name | PP1_WB1_TARGET_PIXEL_FORMAT |
|---|---|
| Offset Address | 0x000000A208 |
| Absolute Address | 0x00FD4BA208 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | WB1 Target Pixel Format Register |
PP1_WB1_TARGET_PIXEL_FORMAT (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
| WB1_TARGET_PIXEL_FORMAT | 3:0 | rwNormal read/write | 0x0 | Contains the pixel format of the target buffer |