L3_PLL_SS_STEPS_1_MSB (SERDES) Register Description
| Register Name | L3_PLL_SS_STEPS_1_MSB |
|---|---|
| Offset Address | 0x000000E36C |
| Absolute Address | 0x00FD40E36C (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L3_PLL_SS_STEPS_1_MSB (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PLL_SS_STEPS_1_MSB_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| ss_num_of_steps_1_msb_rsvd | 7:3 | roRead-only | 0x0 | Value generated by PCW. |
| ss_num_of_steps_1_msb | 2:0 | rwNormal read/write | 0x0 | Value generated by PCW. |