MASK_DATA_1_MSW (GPIO) Register Description
| Register Name | MASK_DATA_1_MSW |
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| Offset Address | 0x000000000C |
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| Absolute Address |
0x00FF0A000C (GPIO)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Maskable Output Data (GPIO Bank1, MIO, Upper 10 bits) |
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This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 10 bits of bank1, which corresponds to MIO[51:42].
MASK_DATA_1_MSW (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
| MASK_1_MSW | 25:16 | woWrite-only | 0x0 | Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW] |
| Reserved | 15:10 | razRead as zero | 0x0 | Not used, read back as zero |
| DATA_1_MSW | 9:0 | rwNormal read/write | 0 | Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW] |