REQ_ISO_INT_MASK (PMU_GLOBAL) Register Description
| Register Name | REQ_ISO_INT_MASK |
|---|
| Offset Address | 0x0000000314 |
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| Absolute Address |
0x00FFD80314 (PMU_GLOBAL)
|
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| Width | 32 |
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| Type | roRead-only |
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| Reset Value | 0x00000017 |
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| Description | Isolation Request; Interrupt Mask. |
|---|
0: unmasked (enabled). 1: masked (disabled). If the status bit = 1 (asserted interrupt) and the mask bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only. For details on the bit fields, refer to the REQ_ISO_TRIG register description.
REQ_ISO_INT_MASK (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:5 | roRead-only | 0x0 | reserved |
| FP_Locked | 4 | roRead-only | 0x1 | FPD voltage node locked out. |
| Reserved | 3 | roRead-only | 0x0 | reserved |
| PL_NonPCAP | 2 | roRead-only | 0x1 | Isolate PL except allow PCAP accesses. |
| PL | 1 | roRead-only | 0x1 | Isolate PL. |
| FP | 0 | roRead-only | 0x1 | Isolate FPD. |