PLC2 (SATA_AHCI_VENDOR) Register Description
| Register Name | PLC2 |
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| Offset Address | 0x0000000038 |
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| Absolute Address |
0x00FD0C00D8 (SATA_AHCI_VENDOR)
|
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| Width | 32 |
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| Type | rwNormal read/write |
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| Reset Value | 0x00000000 |
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| Description | Port LinkCfg2 |
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Controls the configuration of the Link Layer for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
PLC2 (SATA_AHCI_VENDOR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| OP | 31:0 | rwNormal read/write | 0x0 | Override Primitive (OP): This 32-bit bus specifies the data to be used in the overriding primitive debug logic, described in the definition of LinkCfg1 above. |