GICP3_IRQ_TRIGGER (LPD_SLCR) Register Description
| Register Name | GICP3_IRQ_TRIGGER |
|---|---|
| Offset Address | 0x000000804C |
| Absolute Address | 0x00FF41804C (LPD_SLCR) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt. |
GICP3_IRQ_TRIGGER (LPD_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| src31 | 31 | woWrite-only | 0x0 | FPD DMA interrupt for channel 3 |
| src30 | 30 | woWrite-only | 0x0 | FPD DMA interrupt for channel 2 |
| src29 | 29 | woWrite-only | 0x0 | FPD DMA interrupt for channel 1 |
| src28 | 28 | woWrite-only | 0x0 | FPD DMA interrupt for channel 0 (GDMA) |
| src27 | 27 | woWrite-only | 0x0 | APM_FPD: Ord of all APMs for FPD |
| src26 | 26 | woWrite-only | 0x0 | DPDMA interrupt |
| src25 | 25 | woWrite-only | 0x0 | ATB interrupt for FPD |
| src24 | 24 | woWrite-only | 0x0 | FPD_APB_INT: ORd of all APB interrupts from LPD |
| src23 | 23 | woWrite-only | 0x0 | Display port general purpose interrupt |
| src22 | 22 | woWrite-only | 0x0 | PCIE misc (error etc) interrupts |
| src21 | 21 | woWrite-only | 0x0 | PCIE Bridge DMA interrupts |
| src20 | 20 | woWrite-only | 0x0 | PCIE legacy (INTA/BC/D) interrupts |
| src19 | 19 | woWrite-only | 0x0 | PCIE_MSI[1]=PCIe interrupt for MSI vectors 63 to 32 |
| src18 | 18 | woWrite-only | 0x0 | PCIE_MSI[0]=PCIe interrupt for MSI vectors 31 to 0 |
| src17 | 17 | woWrite-only | 0x0 | FPD Top Level Watch Dog Timer Interrupt. This is Edge trigger interrupt and Interrupt pulse width case be prograbble window from 40ns to 320ns. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src16 | 16 | woWrite-only | 0x0 | DDR controller subsystem interrupt |
| src15 | 15 | woWrite-only | 0x0 | Bit 7 of PL_PS IRQ1. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src14 | 14 | woWrite-only | 0x0 | Bit 6 of PL_PS IRQ1. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src13 | 13 | woWrite-only | 0x0 | Bit 5 of PL_PS IRQ1. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src12 | 12 | woWrite-only | 0x0 | Bit 4 of PL_PS IRQ1. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src11 | 11 | woWrite-only | 0x0 | Bit 3 of PL_PS IRQ1. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src10 | 10 | woWrite-only | 0x0 | Bit 2 of PL_PS IRQ1. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src9 | 9 | woWrite-only | 0x0 | Bit 1 of PL_PS IRQ1. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src8 | 8 | woWrite-only | 0x0 | Bit 0 of PL_PS IRQ1. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src0 | 0 | woWrite-only | 0x0 | Bit 7 of PL_PS IRQ0. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |