INT_STAT_1 (GPIO) Register Description
| Register Name | INT_STAT_1 |
|---|---|
| Offset Address | 0x0000000258 |
| Absolute Address | 0x00FF0A0258 (GPIO) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Status (GPIO Bank1, MIO) |
This register operates in exactly the same manner as INT_STAT_0, except that it reflects bank1, which corresponds to MIO[51:26].
INT_STAT_1 (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
| INT_STATUS_1 | 25:0 | wtcReadable, write a 1 to clear | 0x0 | Interrupt status Upon read: 0: no interrupt 1: interrupt event has occurred Upon write: 0: no action 1: clear interrupt status bit Each bit configures the corresponding pin within the 26-bit bank |