L0_TX_ANA_TM_15 (SERDES) Register Description
| Register Name | L0_TX_ANA_TM_15 |
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| Offset Address | 0x000000003C |
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| Absolute Address |
0x00FD40003C (SERDES)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Override for TX Swing, enable for rx detection and enable for rx detection charge and discharge |
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NOTE: the register descriptions for public registers are not available except in the ODS files.
L0_TX_ANA_TM_15 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| TX_ANA_TM_15_31_8_rsvd | 31:8 | roRead-only | 0x0 | Reserved |
| pipe_TX_Swing | 7 | rwNormal read/write | 0x0 | PIPE TX Swing (0- Full Swing/1- Half Swing) |
| force_pipe_TX_Swing | 6 | rwNormal read/write | 0x0 | Enable/disable PIPE TX Swing |
| pipe_TX_rxdet_discharge | 5 | rwNormal read/write | 0x0 | RX detection discharge |
| force_pipe_TX_rxdet_discharge | 4 | rwNormal read/write | 0x0 | Enable/disable RX detection discharge |
| pipe_TX_rxdet_charge | 3 | rwNormal read/write | 0x0 | RX detection charge |
| force_pipe_TX_rxdet_charge | 2 | rwNormal read/write | 0x0 | Enable/disable RX detection charge |
| pipe_TX_enable_rxdet | 1 | rwNormal read/write | 0x0 | RX detection |
| force_pipe_TX_enable_rxdet | 0 | rwNormal read/write | 0x0 | Enable/disable RX detection |