PIDR2 (STM) Register Description
| Register Name | PIDR2 |
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| Offset Address | 0x0000000FE8 |
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| Absolute Address |
0x00FE9C0FE8 (CORESIGHT_SOC_STM)
|
|---|
| Width | 32 |
|---|
| Type | roRead-only |
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| Reset Value | 0x0000001B |
|---|
| Description | PID - Design Identity and Product Revision. |
|---|
Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision.
PIDR2 (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| REVISION | 7:4 | roRead-only | 0x1 | An incremental value starting at 0x0 for the first design of this component. The value increases by one for both major and minor revisions and is used as a look-up to establish the exact major and minor revision. |
| JEDEC | 3 | roRead-only | 0x1 | Indicates the use of a JEDEC assigned value. This bit is always set. |
| DES_1 | 2:0 | roRead-only | 0x3 | Bits [6:4] of the JEDEC identity code indicating the designer of the component, together with the continuation code. |