RPU_1_ISR (IPI) Register Description
| Register Name | RPU_1_ISR |
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| Offset Address | 0x0000020010 |
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| Absolute Address |
0x00FF320010 (IPI)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Ch 2 Interrupt Status and Clear (receiver). Default RPU1. |
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The RPU1 target processor reads this register along with its mask register to determine which initiator(s) caused the IPI interrupt. READ: 0: inactive. 1: active. WRITE: 0: no effect. 1: clears this bit. Note: If a Status bit is 1 and its Mask is 0, then the interrupt signal is asserted to the target interrupt controller. Note: These bit values can be read by the initiator using the initiators Observation register. Beware that this does not provide the initiator with the state of the target's Mask register.
RPU_1_ISR (IPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:28 | roRead-only | 0x0 | reserved |
| PL_3 | 27 | wtcReadable, write a 1 to clear | 0x0 | Ch 10. Default to PL IPI3. |
| PL_2 | 26 | wtcReadable, write a 1 to clear | 0x0 | Ch 9. Default to PL IPI2. |
| PL_1 | 25 | wtcReadable, write a 1 to clear | 0x0 | Ch 8. Default to PL IPI1. |
| PL_0 | 24 | wtcReadable, write a 1 to clear | 0x0 | Ch 7. Default to PL IPI0. |
| Reserved | 23:20 | roRead-only | 0x0 | reserved |
| PMU_3 | 19 | wtcReadable, write a 1 to clear | 0x0 | Ch 6: PMU IPI3. |
| PMU_2 | 18 | wtcReadable, write a 1 to clear | 0x0 | Ch 5: PMU IPI2. |
| PMU_1 | 17 | wtcReadable, write a 1 to clear | 0x0 | Ch 4: PMU IPI1. |
| PMU_0 | 16 | wtcReadable, write a 1 to clear | 0x0 | Ch 3: PMU IPI0. |
| Reserved | 15:10 | roRead-only | 0x0 | reserved |
| RPU_1 | 9 | wtcReadable, write a 1 to clear | 0x0 | Ch 2. Default to RPU1. |
| RPU_0 | 8 | wtcReadable, write a 1 to clear | 0x0 | Ch 1. Default to RPU0. |
| Reserved | 7:1 | roRead-only | 0x0 | reserved |
| APU | 0 | wtcReadable, write a 1 to clear | 0x0 | Ch 0. Default to APU MPCore. |