ERR_CTRL (CRL_APB) Register Description
| Register Name | ERR_CTRL |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FF5E0000 (CRL_APB) |
| Width | 1 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | SLVERR Error Signal Enable. |
ERR_CTRL (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| slverr_enable | 0 | rwNormal read/write | 0x0 | Accesses to an unimplemented register asserts the SLVERR error signal on the APB bus interface and generates an interrupt. 0: disable. 1: enable. Regardless of the setting of the [slverr_enable] bit setting: * The [addr_decode_err] interrupt bit is set in the interrupt status register. * APB writes are ignored and reads returns 0. |