ctrl (RSA_CORE) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ctrl (RSA_CORE) Register Description

Register Namectrl
Offset Address0x0000000010
Absolute Address 0x00FFCE0010 (RSA_CORE)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionRSA Control

ctrl (RSA_CORE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
len_code 7:4woWrite-only0x0Length code:
0xA: RSA2048
0xC: RSA4096
All others: Reserved
done_clr_abort 3woWrite-only0x0Clear the done signal from STATUS, abort the current operation.
opcode 2:0woWrite-only0x0Operation code:
0x0: NOP
0x1: Exponentiation
0x5: Exponentiation using R*R mod M
All others: Reserved