APU_TRIG (IPI) Register Description
Register Name | APU_TRIG |
---|---|
Offset Address | 0x0000000000 |
Absolute Address | 0x00FF300000 (IPI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Ch 0 Interrupt Trigger (sender). Default APU MPCore. |
The APU initiates an interrrupt to another processor by writing a 1 to a bit. This asserts a signal that sets a bit in the target ISR register. Write-Only: 0: no effect. 1: set interrupt bit in target ISR register.
APU_TRIG (IPI) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:28 | roRead-only | 0x0 | reserved |
PL_3 | 27 | woWrite-only | 0x0 | Ch 10. Default to PL IPI3. |
PL_2 | 26 | woWrite-only | 0x0 | Ch 9. Default to PL IPI2. |
PL_1 | 25 | woWrite-only | 0x0 | Ch 8. Default to PL IPI1. |
PL_0 | 24 | woWrite-only | 0x0 | Ch 7. Default to PL IPI0. |
Reserved | 23:20 | roRead-only | 0x0 | reserved |
PMU_3 | 19 | woWrite-only | 0x0 | Ch 6: PMU IPI3. |
PMU_2 | 18 | woWrite-only | 0x0 | Ch 5: PMU IPI2. |
PMU_1 | 17 | woWrite-only | 0x0 | Ch 4: PMU IPI1. |
PMU_0 | 16 | woWrite-only | 0x0 | Ch 3: PMU IPI0. |
Reserved | 15:10 | roRead-only | 0x0 | reserved |
RPU_1 | 9 | woWrite-only | 0x0 | Ch 2. Default to RPU1. |
RPU_0 | 8 | woWrite-only | 0x0 | Ch 1. Default to RPU0. |
Reserved | 7:1 | roRead-only | 0x0 | reserved |
APU | 0 | woWrite-only | 0x0 | Ch 0. Default to APU MPCore. |