DSCCR (R5_DBG_1) Register Description
| Register Name | DSCCR |
|---|---|
| Offset Address | 0x0000000028 |
| Absolute Address | 0x00FEBF2028 (CORESIGHT_R5_DBG_1) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Debug State Cache Control Register |
DSCCR (R5_DBG_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| nWT | 2 | rwNormal read/write | 0x0 | Not write-through: 1 = normal operation of regions marked as write-back in debug state 0 = force write-through behavior for regions marked as write-back in debug state |
| nIL | 1 | rwNormal read/write | 0x0 | Instruction cache line-fill: 1 = normal operation of L1 instruction cache in debug state 0 = L1 instruction cache line-fills disabled in debug state |
| nDL | 0 | rwNormal read/write | 0x0 | Data cache line-fill: 1 = normal operation of L1 data cache in debug state 0 = L1 data cache line-fills disabled in debug state |