ERROR_INT_MASK_1 (PMU_GLOBAL) Register Description
| Register Name | ERROR_INT_MASK_1 |
|---|---|
| Offset Address | 0x0000000534 |
| Absolute Address | 0x00FFD80534 (PMU_GLOBAL) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x0FFF32FF |
| Description | System Errors to PMU; Interrupt Mask, Reg 1. |
0: unmasked (enabled). 1: masked (disabled). If the status bit = 1 (asserted interrupt) and the mask bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only. For details on the bit fields, refer to the ERROR_STATUS_1 register description. The [CLK_MON] and [CSU_SWDT] bits are reset only by the PS_POR_B reset signal pin.
ERROR_INT_MASK_1 (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CSU_SWDT | 27 | roRead-only | 0x1 | CSU_SWDT timeout. Bit is reset only by the PS_POR_B reset signal pin. |
| CLK_MON | 26 | roRead-only | 0x1 | Clock Monitor (ClkMon). Bit is reset only by the PS_POR_B reset signal pin. |
| XMPU | 25:24 | roRead-only | 0x3 | XMPU and XPPU error signals. |
| PWR_SUPPLY | 23:16 | roRead-only | 0xFF | Eight (8) PS VCC and VCCO power supplies. |
| Reserved | 15:14 | roRead-only | 0x0 | reserved |
| FPD_SWDT | 13 | roRead-only | 0x1 | FPD_SWDT timeout. |
| LPD_SWDT | 12 | roRead-only | 0x1 | LPD_SWDT timeout. |
| Reserved | 11:10 | roRead-only | 0x0 | reserved |
| RPU_CCF | 9 | roRead-only | 0x1 | RPU common cause failures. |
| Reserved | 8 | roRead-only | 0x0 | reserved |
| RPU_LS | 7:6 | roRead-only | 0x3 | RPU lockstep error. |
| FPD_TEMP | 5 | roRead-only | 0x1 | FPD over tempurature alarm. |
| LPD_TEMP | 4 | roRead-only | 0x1 | LPD over tempurature alarm. |
| RPU1 | 3 | roRead-only | 0x1 | RPU1 RAM (all ECC errors). |
| RPU0 | 2 | roRead-only | 0x1 | RPU0 RAM (all ECC errors). |
| OCM_ECC | 1 | roRead-only | 0x1 | OCM (uncorrectable only). |
| DDR_ECC | 0 | roRead-only | 0x1 | DDR (uncorrectable only). |