PL3_THR_CNT (CRL_APB) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

PL3_THR_CNT (CRL_APB) Register Description

Register NamePL3_THR_CNT
Offset Address0x00000000FC
Absolute Address 0x00FF5E00FC (CRL_APB)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionPL Clock 3 Threshold Count Value.

PL3_THR_CNT (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LAST_CNT15:0rwNormal read/write0x0The number of clocks after receiving a trigger that the clocks should stop