INT_MASK_0 (GPIO) Register Description
| Register Name | INT_MASK_0 |
|---|---|
| Offset Address | 0x000000020C |
| Absolute Address | 0x00FF0A020C (GPIO) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x03FFFFFF |
| Description | Interrupt Mask Status (GPIO Bank0, MIO) |
This register shows which bits are currently masked and which are un-masked/enabled. This register is read only, so masks cannot be changed here. Use INT_EN and INT_DIS to change the mask value. This register controls bank0, which corresponds to MIO[25:0].
INT_MASK_0 (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
| INT_MASK_0 | 25:0 | roRead-only | 0x3FFFFFF | Interrupt mask 0: interrupt source enabled 1: interrupt source masked Each bit reports the status for the corresponding pin within the 26-bit bank |