L3_TM_CDR16 (SERDES) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

L3_TM_CDR16 (SERDES) Register Description

Register NameL3_TM_CDR16
Offset Address0x000000DC40
Absolute Address 0x00FD40DC40 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TM_CDR16 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_CDR16_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
UNUSED 7:5roRead-only0x0Value generated by PCW.
ffl_ph0_prop_gain 4:0rwNormal read/write0x0Value generated by PCW.