MIO_PIN_52 (IOU_SLCR) Register Description
| Register Name | MIO_PIN_52 |
|---|---|
| Offset Address | 0x00000000D0 |
| Absolute Address | 0x00FF1800D0 (IOU_SLCR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | MIO Device Pin 52 Multiplexer Controls. |
MIO_PIN_52 (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | rwNormal read/write | 0x0 | reserved |
| L3_SEL | 7:5 | rwNormal read/write | 0x0 | Level 3 Mux Select: 0: GPIO [52] input/output bank 2. 1: CAN1 TX output. 2: I2C1 SCL input/output clock. 3: PJTAG TCK input clock. 4: SPI0 SCLK clock input/output. 5: TTC1 clock input. 6: UART1 TxD output. 7: TracePort clock output. |
| L2_SEL | 4:3 | rwNormal read/write | 0x0 | Level 2 Mux Select: 0: Level 3 Mux output 1: reserved 2: reserved 3: reserved |
| L1_SEL | 2 | rwNormal read/write | 0x0 | Level 1 Mux Select: 0: Level 2 Mux output 1: USB0 ULPI Clock input. |
| L0_SEL | 1 | rwNormal read/write | 0x0 | Level 0 Mux Select: 0: Level 1 Mux output 1: GEM2 RGMII Tx Clock output. |
| Reserved | 0 | rwNormal read/write | 0x0 | reserved |