Modem_sts (UART) Register Description
| Register Name | Modem_sts |
|---|---|
| Offset Address | 0x0000000028 |
| Absolute Address |
0x00FF000028 (UART0) 0x00FF010028 (UART1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Modem Status Register |
The Modem Status register indicates the current state of the control lines from the modem, or peripheral device, to the CPU. In addition, four bits of the modem status register provide change of state or delta information. These bits are set to logic 1 whenever a control input from the modem changes state. In the default configuration, these delta bits are all cleared simultaneously when this register is read. This may be parameterised at compile time such that a one must be written to a bit in order to clear it and a read has no effect.
Modem_sts (UART) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:9 | roRead-only | 0 | Reserved, read as zero, ignored on write. |
| FCMS | 8 | rwNormal read/write | 0 | Flow Control Mode: 0: disabled 1: enabled |
| DCD | 7 | roRead-only | 0 | Data Carrier Detect (DCD) input signal from PL (EMIOUARTxDCDN) status: 0: input is high 1: input is low |
| RI | 6 | roRead-only | 0 | Ring Indicator (RI) input signal from PL (EMIOUARTxRIN) status: 0: input is high 1: input is low |
| DSR | 5 | roRead-only | 0 | Data Set Ready (DSR) input signal from PL (EMIOUARTxDSRN) status: 0: input is high 1: input is low |
| CTS | 4 | roRead-only | 0 | Clear to Send (CTS) input signal from PL (EMIOUARTxCTSN) status: 0: input is high 1: input is low |
| DDCD | 3 | wtcReadable, write a 1 to clear | 0 | Delta Data Carrier Detect status: Indicates a change in state of the EMIOUARTxDCDN input since this bit was last cleared. 0: No change has occurred 1: Change has occurred |
| TERI | 2 | wtcReadable, write a 1 to clear | 0 | Trailing Edge Ring Indicator status: Indicates that the EMIOUARTxRIN input has change from high to low state since this bit was last cleared. 0: No trailing edge has occurred 1: Trailing edge has occurred |
| DDSR | 1 | wtcReadable, write a 1 to clear | 0 | Delta Data Set Ready status: Indicates a change in state of the EMIOUARTxDSRN input since this bit was last cleared. 0: No change has occurred 1: Change has occurred |
| DCTS | 0 | wtcReadable, write a 1 to clear | 0 | Delta Clear To Send status: Indicates a change in state of the EMIOUARTxCTSN input since this bit was last cleared. 0: No change has occurred 1: Change has occurred |