smmu_cb5_pmauthstatus (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

smmu_cb5_pmauthstatus (SMMU500) Register Description

Register Name	smmu_cb5_pmauthstatus
Offset Address	0x0000015FB8
Absolute Address	0x00FD815FB8 (SMMU_GPV)
Width	32
Type	roRead-only
Reset Value	0x00000080
Description	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions

smmu_cb5_pmauthstatus (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
SNI	7	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SNE	6	roRead-only	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SI	5	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SE	4	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSNI	3	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSNE	2	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSI	1	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSE	0	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details