L3_TM_PLL_DIG_33 (SERDES) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

L3_TM_PLL_DIG_33 (SERDES) Register Description

Register NameL3_TM_PLL_DIG_33
Offset Address0x000000E084
Absolute Address 0x00FD40E084 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TM_PLL_DIG_33 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_PLL_DIG_33_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
tm_force_tx_clk_rst_rel 7rwNormal read/write0x0Value generated by PCW.
tm_tx_clk_rst_rel 6rwNormal read/write0x0Value generated by PCW.
tm_clkdist_mux_xcvr_master_rst_en 5rwNormal read/write0x0Value generated by PCW.
tm_force_clkdist_mux_xcvr_master_rst_en 4rwNormal read/write0x0Value generated by PCW.
tm_clkdist_mux_master_clk_sel 3rwNormal read/write0x0Value generated by PCW.
tm_force_clkdist_mux_master_clk_sel 2rwNormal read/write0x0Value generated by PCW.
tm_clkdist_mux_local_clk_sel 1rwNormal read/write0x0Value generated by PCW.
tm_force_clkdist_mux_local_clk_sel 0rwNormal read/write0x0Value generated by PCW.