PLS (SATA_AHCI_VENDOR) Register Description
| Register Name | PLS |
|---|---|
| Offset Address | 0x000000003C |
| Absolute Address | 0x00FD0C00DC (SATA_AHCI_VENDOR) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x3120900A |
| Description | Port Link-layer Status. |
Indicates the status of the Link Layer for either Port 0 or Port 1. The Port monitored is controlled by the value programmed into the Port Config Register. Note: All Status Registers have no predefined Reset value. The value shown in reset is a typical value that will be read after reset but will be dependent on the SERDES status, the actual value read can differ from this.
PLS (SATA_AHCI_VENDOR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SVN | 31:28 | roRead-only | 0x3 | SATA Version (SVN): version of the SATA protocol. 3: GEN3. |
| DMB | 27:24 | roRead-only | 0x1 | DMA Master bus type (DMB): 1: AXI. |
| DMBW | 23:20 | roRead-only | 0x2 | DMA Master bus width (DMBW): 0: 32 bit. 1: 64 bit. 2: 128 bit. |
| SRRN | 19:12 | roRead-only | 0x9 | SATA RTL revision number (SRRN) |
| Reserved | 11:6 | roRead-only | 0x0 | Reserved |
| LLS | 5:0 | roRead-only | 0xA | LAT_LINK_STATE (LLS): These six bits specify the current value of the Link Layer State Machine at the time the Status0 register is read. 0: L_Reset 1: L_Idle 2: HL_SendChkRdy 3: DL_SendChkRdy 4: L_TPMPartial 5: L_TPMSlumber 6: L_RcvWaitFifo 7: L_PMOff 8: L_PMDeny 9: L_NoCommErr 10: L_NoComm 11: L_SendAlign 12: L_SendSOF 13: L_SendData 14: WAIT_FOR_SYNC 15: L_SendCRC 16: L_SendHold 17: L_RcvHold 18: L_SendEOF 19: L_Wait 20: L_ChkPhyRdy 21: L_NoCommPower 22: L_WakeUp1 23: L_WakeUp2 24: L_RcvChkRdy 25: L_RcvData 26: L_BadEnd 27: L_RcvEOF 28: L_SendHoldA 29: L_Hold 30: L_GoodCRC 31: L_GoodEnd 32: BISTALIGN 33: BISTSOF 34: BIST0 35: BIST1 36: L_GoodEndLock 37: OneFSendOneSyncLock 38: SFSendOneSyncLock 39: HL_SendChkRdyLock 40: waitForSyncLock 42: L_NoPmnak |