ATTR_100 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_100 |
|---|---|
| Offset Address | 0x0000000190 |
| Absolute Address | 0x00FD480190 (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x000000E0 |
| Description | ATTR_100 |
This register should only be written to during reset of the PCIe block
ATTR_100 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_dnstream_link_num | 15:8 | rwNormal read/write | 0x0 | Used in downstream facing mode only. Specified the link number that this device will advertise in TS1 and TS2 during link training. |
| attr_exit_loopback_on_ei | 7 | rwNormal read/write | 0x1 | When TRUE allows LTSSM (loopback slave at 2.5GT/s) to exit from Loopback.Active on RX Electrical Idle. When FALSE this optional arc is disabled |
| attr_upstream_facing | 6 | rwNormal read/write | 0x1 | TRUE specifies upstream-facing port. FALSE specifies downstream-facing port. |
| attr_upconfig_capable | 5 | rwNormal read/write | 0x1 | This attribute enables the upconfigure capability when set to TRUE and disables the upconfigure capability when set to FALSE |
| attr_pl_auto_config | 3:1 | rwNormal read/write | 0x0 | Bypass link width negotiation in LTSSM Configuration states. Link will configure to x1, x2, x4 or x8 when the value of this attribute is 100, 101, 110 or 111 respectively. When this attribute is 0xx, link width negotiation will not be bypassed |