SD_ITAPDLY (IOU_SLCR) Register Description
| Register Name | SD_ITAPDLY |
|---|---|
| Offset Address | 0x0000000314 |
| Absolute Address | 0x00FF180314 (IOU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Input Tap Delay Select |
SD_ITAPDLY (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| SD1_ITAPCHGWIN | 25 | rwNormal read/write | 0x0 | This is used to gate the output of the Tap Delay lines so as to avoid glithches being propagated into the Core. This signal should be asserted few clocks before the corectrl_itapdlysel changes and should be asserted for few clocks after. |
| SD1_ITAPDLYENA | 24 | rwNormal read/write | 0x0 | This signal along witht he corectrl_itapdlysel[7:0] selects the the amount of delay to be inserted on the line |
| SD1_ITAPDLYSEL | 23:16 | rwNormal read/write | 0x0 | Selects optimal number of Taps on the rxclk_in line. This is effective only when corectrl_itapdlyena is asserted and Tuning is not enabled. For the SD frequency of - 200 MHz: 30 taps are available 100 MHz: 60 taps are available 50 MHz: 120 taps are available 33 MHz: 180 taps are available |
| Reserved | 15:10 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| SD0_ITAPCHGWIN | 9 | rwNormal read/write | 0x0 | This is used to gate the output of the Tap Delay lines so as to avoid glithches being propagated into the Core. This signal should be asserted few clocks before the corectrl_itapdlysel changes and should be asserted for few clocks after. |
| SD0_ITAPDLYENA | 8 | rwNormal read/write | 0x0 | This signal along witht he corectrl_itapdlysel[7:0] selects the the amount of delay to be inserted on the line |
| SD0_ITAPDLYSEL | 7:0 | rwNormal read/write | 0x0 | Selects optimal number of Taps on the rxclk_in line. This is effective only when corectrl_itapdlyena is asserted and Tuning is not enabled. For the SD frequency of - 200 MHz: 30 taps are available 100 MHz: 60 taps are available 50 MHz: 120 taps are available |