GPU Module - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

GPU Module Description

Module Name	GPU Module
Modules of this Type	GPU
Base Addresses	0x00FD4B0000 (GPU)
Description	Graphics Processing Unit

GPU Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
GP_CONTR_REG_VSCL_START_ADDR	0x0000000000	32	rwNormal read/write	0x00000000	GP ControlRegister VSCL Start Address
GP_CONTR_REG_VSCL_END_ADDR	0x0000000004	32	rwNormal read/write	0x00000000	GP Control Register VSCL End Address
GP_CONTR_REG_PLBCL_START_ADDR	0x0000000008	32	rwNormal read/write	0x00000000	GP Control Register PLBCL Start Address
GP_CONTR_REG_PLBCL_END_ADDR	0x000000000C	32	rwNormal read/write	0x00000000	GP Control Register PLBCL End Address
GP_CONTR_REG_PLB_ALLOC_START_ADDR	0x0000000010	32	rwNormal read/write	0x00000000	GP Control Register PLB Allocate Start Address
GP_CONTR_REG_PLB_ALLOC_END_ADDR	0x0000000014	32	rwNormal read/write	0x00000000	GP Control Register PLB Allocate End Address
GP_CONTR_REG_CMD	0x0000000020	32	woWrite-only	0x00000000	GP Control Register Command
GP_CONTR_REG_INT_RAWSTAT	0x0000000024	32	rwNormal read/write	0x00080000	GP Control Register Interrupt Rawstat
GP_CONTR_REG_INT_CLEAR	0x0000000028	32	woWrite-only	0x00707BFF	GP Control Register Interrupt Clear
GP_CONTR_REG_INT_MASK	0x000000002C	32	woWrite-only	0x00000000	GP Control Register Interrupt Mask
GP_CONTR_REG_INT_STAT	0x0000000030	32	roRead-only	0x00080000	GP Control Register Interrupt Status
GP_CONTR_REG_WRITE_BOUND_LOW	0x0000000034	32	rwNormal read/write	0x00000000	GP Control Register Write Boundary Low
GP_CONTR_REG_WRITE_BOUND_HIGH	0x0000000038	32	rwNormal read/write	0xFFFFFF00	GP Control Register Write Boundary High
GP_CONTR_REG_PERF_CNT_0_ENABLE	0x000000003C	32	rwNormal read/write	0x00000000	GP Control Register Performance Counter 0 Enable
GP_CONTR_REG_PERF_CNT_1_ENABLE	0x0000000040	32	rwNormal read/write	0x00000000	GP Control Register Performance Counter 1 Enable
GP_CONTR_REG_PERF_CNT_0_SRC	0x0000000044	32	rwNormal read/write	0x00000000	GP Control Register Performance Counter 0 Source
GP_CONTR_REG_PERF_CNT_1_SRC	0x0000000048	32	rwNormal read/write	0x00000000	GP Control Register Performance Counter 1 Source
GP_CONTR_REG_PERF_CNT_0_VAL	0x000000004C	32	roRead-only	0x00000000	GP Control Register Performance Counter 0 Value
GP_CONTR_REG_PERF_CNT_1_VAL	0x0000000050	32	roRead-only	0x00000000	GP Control Register Performance Counter 1 Value
GP_CONTR_REG_PERF_CNT_0_LIMIT	0x0000000054	32	rwNormal read/write	0x00000000	GP Control Register Performance Counter 0 Limit
GP_CONTR_REG_PERF_CNT_1_LIMIT	0x0000000058	32	rwNormal read/write	0x00000000	GP Control Register Performance Control 1 Limit
GP_CONTR_REG_STATUS	0x0000000068	32	roRead-only	0x00000000	GP Control Register Status
GP_CONTR_REG_VERSION	0x000000006C	32	roRead-only	0x00000B07	GP Control Register VERSION
GP_CONTR_REG_VSCL_INITIAL_ADDR	0x0000000080	32	roRead-only	0x00000000	GP Control Register VSCL Initial Address
GP_CONTR_REG_PLBCL_INITIAL_ADDR	0x0000000084	32	roRead-only	0x00000000	GP Control Register PLBCL Initial Address
GP_CONTR_REG_WRITE_BOUNDARY_ERROR_ADDR	0x0000000088	32	roRead-only	0x00000000	GP Control Register Write Error Address
GP_CONTR_REG_AXI_BUS_ERROR_STAT	0x0000000094	32	roRead-only	0x00000000	GP Control AXI Bus Error Status
GP_CONTR_REG_WATCHDOG_DISABLE	0x00000000A0	32	rwNormal read/write	0x00000000	GP Control Register Watchdog Disable
GP_CONTR_REG_WATCHDOG_TIMEOUT	0x00000000A4	32	rwNormal read/write	0x000F4240	GP Control Register Watchdog Timeout
VERSION	0x0000001000	32	roRead-only	0xCAC20000	VERSION Register
SIZE	0x0000001004	32	roRead-only	0x00000000	SIZE Register
STATUS	0x0000001008	32	roRead-only	0x00000000	Status Register
COMMAND	0x0000001010	32	woWrite-only	0x00000000	Command Register
CLEAR_PAGE	0x0000001014	32	woWrite-only	0x00000000	Clear Page Register
MAX_READS	0x0000001018	32	rwNormal read/write	0x0000001C	Maximum Reads Register
ENABLE	0x000000101C	32	rwNormal read/write	0x00000000	Enable Register
PERFCNT_SRC0	0x0000001020	32	rwNormal read/write	0x00000000	Performance Counter 0 Source Register
PERFCNT_VAL0	0x0000001024	32	rwNormal read/write	0x00000000	Performance Counter 0 Value Register
PERFCNT_SRC1	0x0000001028	32	rwNormal read/write	0x00000000	Performance Counter 1 Source Register
PERFCNT_VAL1	0x000000102C	32	rwNormal read/write	0x00000000	Performance Counter 1 Value Register
GP_MMU_DTE_ADDR	0x0000003000	32	rwNormal read/write	0x00000000	MMU Current Page Table Address Register
GP_MMU_STATUS	0x0000003004	32	roRead-only	0x00000018	MMU Status Register
GP_MMU_COMMAND	0x0000003008	32	woWrite-only	0x00000000	MMU Command Register
GP_MMU_PAGE_FAULT_ADDR	0x000000300C	32	roRead-only	0x00000000	MMU Logical Address
GP_MMU_ZAP_ONE_LINE	0x0000003010	32	woWrite-only	0x00000000	MMU Zap Cache Line Register
GP_MMU_INT_RAWSTAT	0x0000003014	32	rwNormal read/write	0x00000000	MMU Raw Interrupt Status Register
GP_MMU_INT_CLEAR	0x0000003018	32	woWrite-only	0x00000000	MMU Interrupt Clear Register
GP_MMU_INT_MASK	0x000000301C	32	rwNormal read/write	0x00000000	MMU Interrupt Mask Register
GP_MMU_INT_STATUS	0x0000003020	32	roRead-only	0x00000000	MMU Interrupt Status Register
PP0_MMU_DTE_ADDR	0x0000004000	32	rwNormal read/write	0x00000000	MMU Current Page Table Address Register
PP0_MMU_STATUS	0x0000004004	32	roRead-only	0x00000018	MMU Status Register
PP0_MMU_COMMAND	0x0000004008	32	woWrite-only	0x00000000	MMU Command Register
PP0_MMU_PAGE_FAULT_ADDR	0x000000400C	32	roRead-only	0x00000000	MMU Logical Address
PP0_MMU_ZAP_ONE_LINE	0x0000004010	32	woWrite-only	0x00000000	MMU Zap Cache Line Register
PP0_MMU_INT_RAWSTAT	0x0000004014	32	rwNormal read/write	0x00000000	MMU Raw Interrupt Status Register
PP0_MMU_INT_CLEAR	0x0000004018	32	woWrite-only	0x00000000	MMU Interrupt Clear Register
PP0_MMU_INT_MASK	0x000000401C	32	rwNormal read/write	0x00000000	MMU Interrupt Mask Register
PP0_MMU_INT_STATUS	0x0000004020	32	roRead-only	0x00000000	MMU Interrupt Status Register
PP1_MMU_DTE_ADDR	0x0000005000	32	rwNormal read/write	0x00000000	MMU Current Page Table Address Register
PP1_MMU_STATUS	0x0000005004	32	roRead-only	0x00000018	MMU Status Register
PP1_MMU_COMMAND	0x0000005008	32	woWrite-only	0x00000000	MMU Command Register
PP1_MMU_PAGE_FAULT_ADDR	0x000000500C	32	roRead-only	0x00000000	MMU Logical Address
PP1_MMU_ZAP_ONE_LINE	0x0000005010	32	woWrite-only	0x00000000	MMU Zap Cache Line Register
PP1_MMU_INT_RAWSTAT	0x0000005014	32	rwNormal read/write	0x00000000	MMU Raw Interrupt Status Register
PP1_MMU_INT_CLEAR	0x0000005018	32	woWrite-only	0x00000000	MMU Interrupt Clear Register
PP1_MMU_INT_MASK	0x000000501C	32	rwNormal read/write	0x00000000	MMU Interrupt Mask Register
PP1_MMU_INT_STATUS	0x0000005020	32	roRead-only	0x00000000	MMU Interrupt Status Register
PP0_REND_LIST_ADDR	0x0000008000	32	rwNormal read/write	0x00000000	Renderer List Address Register
PP0_REND_RSW_BASE	0x0000008004	32	rwNormal read/write	0x00000000	Renderer State Word Base Address Register
PP0_REND_VERTEX_BASE	0x0000008008	32	rwNormal read/write	0x00000000	Renderer Vertex Base Register
PP0_FEATURE_ENABLE	0x000000800C	32	rwNormal read/write	0x00000002	Feature Enable Register
PP0_Z_CLEAR_VALUE	0x0000008010	32	rwNormal read/write	0x00000000	Z Clear Value Register
PP0_STENCIL_CLEAR_VALUE	0x0000008014	32	rwNormal read/write	0x00000000	Stencil Clear Value Register
PP0_ABGR_CLEAR_VALUE_0	0x0000008018	32	rwNormal read/write	0x00000000	ABGR Clear Value 0 Register
PP0_ABGR_CLEAR_VALUE_1	0x000000801C	32	rwNormal read/write	0x00000000	ABGR Clear Value 1 Register
PP0_ABGR_CLEAR_VALUE_2	0x0000008020	32	rwNormal read/write	0x00000000	ABGR Clear Value 2 Register
PP0_ABGR_CLEAR_VALUE_3	0x0000008024	32	rwNormal read/write	0x00000000	ABGR Clear Value 3 Register
PP0_BOUNDING_BOX_LEFT_RIGHT	0x0000008028	32	rwNormal read/write	0x00000000	Bounding Box Left Right Register
PP0_BOUNDING_BOX_BOTTOM	0x000000802C	32	rwNormal read/write	0x00000000	Bounding Box Bottom Register
PP0_FS_STACK_ADDR	0x0000008030	32	rwNormal read/write	0x00000000	FS Stack Address Register
PP0_FS_STACK_SIZE_AND_INIT_VAL	0x0000008034	32	rwNormal read/write	0x00000000	FS Stack Size and Initial Value Register
PP0_ORIGIN_OFFSET_X	0x0000008040	32	rwNormal read/write	0x00000000	Origin Offset X Register
PP0_ORIGIN_OFFSET_Y	0x0000008044	32	rwNormal read/write	0x00000000	Origin Offset Y Register
PP0_SUBPIXEL_SPECIFIER	0x0000008048	32	rwNormal read/write	0x00000075	Subpixel Specifier Register
PP0_TIEBREAK_MODE	0x000000804C	32	rwNormal read/write	0x00000000	Tiebreak mode Register
PP0_PLIST_CONFIG	0x0000008050	32	rwNormal read/write	0x00000000	Polygon List Format Register
PP0_SCALING_CONFIG	0x0000008054	32	rwNormal read/write	0x00000000	Scaling Register
PP0_TILEBUFFER_BITS	0x0000008058	32	rwNormal read/write	0x00000000	Tilebuffer configuration Register
PP0_WB0_SOURCE_SELECT	0x0000008100	32	rwNormal read/write	0x00000000	WB0 Source Select Register
PP0_WB0_TARGET_ADDR	0x0000008104	32	rwNormal read/write	0x00000000	WB0 Target Address Register
PP0_WB0_TARGET_PIXEL_FORMAT	0x0000008108	32	rwNormal read/write	0x00000000	WB0 Target Pixel Format Register
PP0_WB0_TARGET_AA_FORMAT	0x000000810C	32	rwNormal read/write	0x00000000	WB0 Target AA Format Register
PP0_WB0_TARGET_LAYOUT	0x0000008110	32	rwNormal read/write	0x00000000	WB0 Target Layout
PP0_WB0_TARGET_SCANLINE_LENGTH	0x0000008114	32	rwNormal read/write	0x00000000	WB0 Target Scanline Length
PP0_WB0_TARGET_FLAGS	0x0000008118	32	rwNormal read/write	0x00000000	WB0 Target Flags Register
PP0_WB0_MRT_ENABLE	0x000000811C	32	rwNormal read/write	0x00000000	WB0 MRT Enable Register
PP0_WB0_MRT_OFFSET	0x0000008120	32	rwNormal read/write	0x00000000	WB0 MRT Offset Register
PP0_WB0_GLOBAL_TEST_ENABLE	0x0000008124	32	rwNormal read/write	0x00000000	WB0 Global Test Enable Register
PP0_WB0_GLOBAL_TEST_REF_VALUE	0x0000008128	32	rwNormal read/write	0x00000000	WB0 Global Test Reference Value Register
PP0_WB0_GLOBAL_TEST_CMP_FUNC	0x000000812C	32	rwNormal read/write	0x00000000	WB0 Global Test Compare Function Register
PP0_WB1_SOURCE_SELECT	0x0000008200	32	rwNormal read/write	0x00000000	WB1 Source Select Register
PP0_WB1_TARGET_ADDR	0x0000008204	32	rwNormal read/write	0x00000000	WB1 Target Address Register
PP0_WB1_TARGET_PIXEL_FORMAT	0x0000008208	32	rwNormal read/write	0x00000000	WB1 Target Pixel Format Register
PP0_WB1_TARGET_AA_FORMAT	0x000000820C	32	rwNormal read/write	0x00000000	WB1 Target AA Format Register
PP0_WB1_TARGET_LAYOUT	0x0000008210	32	rwNormal read/write	0x00000000	WB1 Target Layout
PP0_WB1_TARGET_SCANLINE_LENGTH	0x0000008214	32	rwNormal read/write	0x00000000	WB1 Target Scanline Length
PP0_WB1_TARGET_FLAGS	0x0000008218	32	rwNormal read/write	0x00000000	WB1 Target Flags Register
PP0_WB1_MRT_ENABLE	0x000000821C	32	rwNormal read/write	0x00000000	WB1 MRT Enable Register
PP0_WB1_MRT_OFFSET	0x0000008220	32	rwNormal read/write	0x00000000	WB1 MRT Offset Register
PP0_WB1_GLOBAL_TEST_ENABLE	0x0000008224	32	rwNormal read/write	0x00000000	WB1 Global Test Enable Register
PP0_WB1_GLOBAL_TEST_REF_VALUE	0x0000008228	32	rwNormal read/write	0x00000000	WB1 Global Test Reference Value Register
PP0_WB1_GLOBAL_TEST_CMP_FUNC	0x000000822C	32	rwNormal read/write	0x00000000	WB1 Global Test Compare Function Register
PP0_WB2_SOURCE_SELECT	0x0000008300	32	rwNormal read/write	0x00000000	WB2 Source Select Register
PP0_WB2_TARGET_ADDR	0x0000008304	32	rwNormal read/write	0x00000000	WB2 Target Address Register
PP0_WB2_TARGET_PIXEL_FORMAT	0x0000008308	32	rwNormal read/write	0x00000000	WB2 Target Pixel Format Register
PP0_WB2_TARGET_AA_FORMAT	0x000000830C	32	rwNormal read/write	0x00000000	WB2 Target AA Format Register
PP0_WB2_TARGET_LAYOUT	0x0000008310	32	rwNormal read/write	0x00000000	WB2 Target Layout
PP0_WB2_TARGET_SCANLINE_LENGTH	0x0000008314	32	rwNormal read/write	0x00000000	WB2 Target Scanline Length
PP0_WB2_TARGET_FLAGS	0x0000008318	32	rwNormal read/write	0x00000000	WB2 Target Flags Register
PP0_WB2_MRT_ENABLE	0x000000831C	32	rwNormal read/write	0x00000000	WB2 MRT Enable Register
PP0_WB2_MRT_OFFSET	0x0000008320	32	rwNormal read/write	0x00000000	WB2 MRT Offset Register
PP0_WB2_GLOBAL_TEST_ENABLE	0x0000008324	32	rwNormal read/write	0x00000000	WB2 Global Test Enable Register
PP0_WB2_GLOBAL_TEST_REF_VALUE	0x0000008328	32	rwNormal read/write	0x00000000	WB2 Global Test Reference Value Register
PP0_WB2_GLOBAL_TEST_CMP_FUNC	0x000000832C	32	rwNormal read/write	0x00000000	WB2 Global Test Compare Function Register
PP0_VERSION	0x0000009000	32	roRead-only	0x00CD0007	Version Register
PP0_CURRENT_REND_LIST_ADDR	0x0000009004	32	rwNormal read/write	0x00000000	Current Renderer List Address Register
PP0_STATUS	0x0000009008	32	rwNormal read/write	0x00000000	Pixel Processor Status Register
PP0_CTRL_MGMT	0x000000900C	32	woWrite-only	0x00000000	Control Management Register
PP0_LAST_TILE_POS_START	0x0000009010	32	roRead-only	0x00000000	Last Tile Where Processing Started Register
PP0_LAST_TILE_POS_END	0x0000009014	32	roRead-only	0x00000000	Last Tile Where Processing Completed Register
PP0_INT_RAWSTAT	0x0000009020	32	rwNormal read/write	0x00001000	Interrupt Rawstat Register
PP0_INT_CLEAR	0x0000009024	32	woWrite-only	0x00000000	Interrupt Clear Register
PP0_INT_MASK	0x0000009028	32	rwNormal read/write	0x00000FFF	Interrupt Mask Register
PP0_INT_STATUS	0x000000902C	32	rwNormal read/write	0x00001000	Interrupt Status Register
PP0_WRITE_BOUNDARY_ENABLE	0x0000009040	32	rwNormal read/write	0x00000000	Write Boundary Enable Register
PP0_WRITE_BOUNDARY_LOW	0x0000009044	32	rwNormal read/write	0x00000000	Write Boundary Low Register
PP0_WRITE_BOUNDARY_HIGH	0x0000009048	32	rwNormal read/write	0x00000000	Write Boundary High Register
PP0_WRITE_BOUNDARY_ADDRESS	0x000000904C	32	rwNormal read/write	0x00000000	Write Boundary Address Register
PP0_BUS_ERROR_STATUS	0x0000009050	32	rwNormal read/write	0x00000000	Bus Error Status Register
PP0_WATCHDOG_DISABLE	0x0000009060	32	rwNormal read/write	0x00000000	Watchdog Disable Register
PP0_WATCHDOG_TIMEOUT	0x0000009064	32	rwNormal read/write	0x00000000	Watchdog Timeout Register
PP0_PERF_CNT_0_ENABLE	0x0000009080	32	rwNormal read/write	0x00000000	Performance Counter 0 Enable Register
PP0_PERF_CNT_0_SRC	0x0000009084	32	rwNormal read/write	0x00000000	Performance Counter 0 SRC Register
PP0_PERF_CNT_0_LIMIT	0x0000009088	32	rwNormal read/write	0x00000000	Performance Counter 0 Limit Register
PP0_PERF_CNT_0_VALUE	0x000000908C	32	rwNormal read/write	0x00000000	Performance Counter 0 Value Register
PP0_PERF_CNT_1_ENABLE	0x00000090A0	32	rwNormal read/write	0x00000000	Performance Counter 0 Enable Register
PP0_PERF_CNT_1_SRC	0x00000090A4	32	rwNormal read/write	0x00000000	Performance Counter 1 SRC Register
PP0_PERF_CNT_1_LIMIT	0x00000090A8	32	rwNormal read/write	0x00000000	Performance Counter 1 Limit Register
PP0_PERF_CNT_1_VALUE	0x00000090AC	32	rwNormal read/write	0x00000000	Performance Counter 1 Value Register
PP0_PERFMON_CONTR	0x00000090B0	32	rwNormal read/write	0x00000000	Performance Monitor Control Register
PP0_PERFMON_BASE	0x00000090B4	32	rwNormal read/write	0x00000000	Performance Monitor Base Address Register
PP1_REND_LIST_ADDR	0x000000A000	32	rwNormal read/write	0x00000000	Renderer List Address Register
PP1_REND_RSW_BASE	0x000000A004	32	rwNormal read/write	0x00000000	Renderer State Word Base Address Register
PP1_REND_VERTEX_BASE	0x000000A008	32	rwNormal read/write	0x00000000	Renderer Vertex Base Register
PP1_FEATURE_ENABLE	0x000000A00C	32	rwNormal read/write	0x00000000	Feature Enable Register
PP1_Z_CLEAR_VALUE	0x000000A010	32	rwNormal read/write	0x00000000	Z Clear Value Register
PP1_STENCIL_CLEAR_VALUE	0x000000A014	32	rwNormal read/write	0x00000000	Stencil Clear Value Register
PP1_ABGR_CLEAR_VALUE_0	0x000000A018	32	rwNormal read/write	0x00000000	ABGR Clear Value 0 Register
PP1_ABGR_CLEAR_VALUE_1	0x000000A01C	32	rwNormal read/write	0x00000000	ABGR Clear Value 1 Register
PP1_ABGR_CLEAR_VALUE_2	0x000000A020	32	rwNormal read/write	0x00000000	ABGR Clear Value 2 Register
PP1_ABGR_CLEAR_VALUE_3	0x000000A024	32	rwNormal read/write	0x00000000	ABGR Clear Value 3 Register
PP1_BOUNDING_BOX_LEFT_RIGHT	0x000000A028	32	rwNormal read/write	0x00000000	Bounding Box Left Right Register
PP1_BOUNDING_BOX_BOTTOM	0x000000A02C	32	rwNormal read/write	0x00000000	Bounding Box Bottom Register
PP1_FS_STACK_ADDR	0x000000A030	32	rwNormal read/write	0x00000000	FS Stack Address Register
PP1_FS_STACK_SIZE_AND_INIT_VAL	0x000000A034	32	rwNormal read/write	0x00000000	FS Stack Size and Initial Value Register
PP1_ORIGIN_OFFSET_X	0x000000A040	32	rwNormal read/write	0x00000000	Origin Offset X Register
PP1_ORIGIN_OFFSET_Y	0x000000A044	32	rwNormal read/write	0x00000000	Origin Offset Y Register
PP1_SUBPIXEL_SPECIFIER	0x000000A048	32	rwNormal read/write	0x00000000	Subpixel Specifier Register
PP1_TIEBREAK_MODE	0x000000A04C	32	rwNormal read/write	0x00000000	Tiebreak mode Register
PP1_PLIST_CONFIG	0x000000A050	32	rwNormal read/write	0x00000000	Polygon List Format Register
PP1_SCALING_CONFIG	0x000000A054	32	rwNormal read/write	0x00000000	Scaling Register
PP1_TILEBUFFER_BITS	0x000000A058	32	rwNormal read/write	0x00000000	Tilebuffer configuration Register
PP1_WB0_SOURCE_SELECT	0x000000A100	32	rwNormal read/write	0x00000000	WB0 Source Select Register
PP1_WB0_TARGET_ADDR	0x000000A104	32	rwNormal read/write	0x00000000	WB0 Target Address Register
PP1_WB0_TARGET_PIXEL_FORMAT	0x000000A108	32	rwNormal read/write	0x00000000	WB0 Target Pixel Format Register
PP1_WB0_TARGET_AA_FORMAT	0x000000A10C	32	rwNormal read/write	0x00000000	WB0 Target AA Format Register
PP1_WB0_TARGET_LAYOUT	0x000000A110	32	rwNormal read/write	0x00000000	WB0 Target Layout
PP1_WB0_TARGET_SCANLINE_LENGTH	0x000000A114	32	rwNormal read/write	0x00000000	WB0 Target Scanline Length
PP1_WB0_TARGET_FLAGS	0x000000A118	32	rwNormal read/write	0x00000000	WB0 Target Flags Register
PP1_WB0_MRT_ENABLE	0x000000A11C	32	rwNormal read/write	0x00000000	WB0 MRT Enable Register
PP1_WB0_MRT_OFFSET	0x000000A120	32	rwNormal read/write	0x00000000	WB0 MRT Offset Register
PP1_WB0_GLOBAL_TEST_ENABLE	0x000000A124	32	rwNormal read/write	0x00000000	WB0 Global Test Enable Register
PP1_WB0_GLOBAL_TEST_REF_VALUE	0x000000A128	32	rwNormal read/write	0x00000000	WB0 Global Test Reference Value Register
PP1_WB0_GLOBAL_TEST_CMP_FUNC	0x000000A12C	32	rwNormal read/write	0x00000000	WB0 Global Test Compare Function Register
PP1_WB1_SOURCE_SELECT	0x000000A200	32	rwNormal read/write	0x00000000	WB1 Source Select Register
PP1_WB1_TARGET_ADDR	0x000000A204	32	rwNormal read/write	0x00000000	WB1 Target Address Register
PP1_WB1_TARGET_PIXEL_FORMAT	0x000000A208	32	rwNormal read/write	0x00000000	WB1 Target Pixel Format Register
PP1_WB1_TARGET_AA_FORMAT	0x000000A20C	32	rwNormal read/write	0x00000000	WB1 Target AA Format Register
PP1_WB1_TARGET_LAYOUT	0x000000A210	32	rwNormal read/write	0x00000000	WB1 Target Layout
PP1_WB1_TARGET_SCANLINE_LENGTH	0x000000A214	32	rwNormal read/write	0x00000000	WB1 Target Scanline Length
PP1_WB1_TARGET_FLAGS	0x000000A218	32	rwNormal read/write	0x00000000	WB1 Target Flags Register
PP1_WB1_MRT_ENABLE	0x000000A21C	32	rwNormal read/write	0x00000000	WB1 MRT Enable Register
PP1_WB1_MRT_OFFSET	0x000000A220	32	rwNormal read/write	0x00000000	WB1 MRT Offset Register
PP1_WB1_GLOBAL_TEST_ENABLE	0x000000A224	32	rwNormal read/write	0x00000000	WB1 Global Test Enable Register
PP1_WB1_GLOBAL_TEST_REF_VALUE	0x000000A228	32	rwNormal read/write	0x00000000	WB1 Global Test Reference Value Register
PP1_WB1_GLOBAL_TEST_CMP_FUNC	0x000000A22C	32	rwNormal read/write	0x00000000	WB1 Global Test Compare Function Register
PP1_WB2_SOURCE_SELECT	0x000000A300	32	rwNormal read/write	0x00000000	WB2 Source Select Register
PP1_WB2_TARGET_ADDR	0x000000A304	32	rwNormal read/write	0x00000000	WB2 Target Address Register
PP1_WB2_TARGET_PIXEL_FORMAT	0x000000A308	32	rwNormal read/write	0x00000000	WB2 Target Pixel Format Register
PP1_WB2_TARGET_AA_FORMAT	0x000000A30C	32	rwNormal read/write	0x00000000	WB2 Target AA Format Register
PP1_WB2_TARGET_LAYOUT	0x000000A310	32	rwNormal read/write	0x00000000	WB2 Target Layout
PP1_WB2_TARGET_SCANLINE_LENGTH	0x000000A314	32	rwNormal read/write	0x00000000	WB2 Target Scanline Length
PP1_WB2_TARGET_FLAGS	0x000000A318	32	rwNormal read/write	0x00000000	WB2 Target Flags Register
PP1_WB2_MRT_ENABLE	0x000000A31C	32	rwNormal read/write	0x00000000	WB2 MRT Enable Register
PP1_WB2_MRT_OFFSET	0x000000A320	32	rwNormal read/write	0x00000000	WB2 MRT Offset Register
PP1_WB2_GLOBAL_TEST_ENABLE	0x000000A324	32	rwNormal read/write	0x00000000	WB2 Global Test Enable Register
PP1_WB2_GLOBAL_TEST_REF_VALUE	0x000000A328	32	rwNormal read/write	0x00000000	WB2 Global Test Reference Value Register
PP1_WB2_GLOBAL_TEST_CMP_FUNC	0x000000A32C	32	rwNormal read/write	0x00000000	WB2 Global Test Compare Function Register
PP1_VERSION	0x000000B000	32	rwNormal read/write	0x00CD0007	Version Register
PP1_CURRENT_REND_LIST_ADDR	0x000000B004	32	rwNormal read/write	0x00000000	Current Renderer List Address Register
PP1_STATUS	0x000000B008	32	rwNormal read/write	0x00000000	Pixel Processor Status Register
PP1_CTRL_MGMT	0x000000B00C	32	rwNormal read/write	0x00000000	Control Management Register
PP1_LAST_TILE_POS_START	0x000000B010	32	rwNormal read/write	0x00000000	Last Tile Where Processing Started Register
PP1_LAST_TILE_POS_END	0x000000B014	32	rwNormal read/write	0x00000000	Last Tile Where Processing Completed Register
PP1_INT_RAWSTAT	0x000000B020	32	rwNormal read/write	0x00000000	Interrupt Rawstat Register
PP1_INT_CLEAR	0x000000B024	32	rwNormal read/write	0x00000000	Interrupt Clear Register
PP1_INT_MASK	0x000000B028	32	rwNormal read/write	0x00000FFF	Interrupt Mask Register
PP1_INT_STATUS	0x000000B02C	32	rwNormal read/write	0x00000000	Interrupt Status Register
PP1_WRITE_BOUNDARY_ENABLE	0x000000B040	32	rwNormal read/write	0x00000000	Write Boundary Enable Register
PP1_WRITE_BOUNDARY_LOW	0x000000B044	32	rwNormal read/write	0x00000000	Write Boundary Low Register
PP1_WRITE_BOUNDARY_HIGH	0x000000B048	32	rwNormal read/write	0x00000000	Write Boundary High Register
PP1_WRITE_BOUNDARY_ADDRESS	0x000000B04C	32	rwNormal read/write	0x00000000	Write Boundary Address Register
PP1_BUS_ERROR_STATUS	0x000000B050	32	rwNormal read/write	0x00000000	Bus Error Status Register
PP1_WATCHDOG_DISABLE	0x000000B060	32	rwNormal read/write	0x00000000	Watchdog Disable Register
PP1_WATCHDOG_TIMEOUT	0x000000B064	32	rwNormal read/write	0x00000000	Watchdog Timeout Register
PP1_PERF_CNT_0_ENABLE	0x000000B080	32	rwNormal read/write	0x00000000	WB2 Global Test Compare Function Register
PP1_PERF_CNT_0_SRC	0x000000B084	32	rwNormal read/write	0x00000000	Performance Counter 0 SRC Register
PP1_PERF_CNT_0_LIMIT	0x000000B088	32	rwNormal read/write	0x00000000	Performance Counter 0 Limit Register
PP1_PERF_CNT_0_VALUE	0x000000B08C	32	rwNormal read/write	0x00000000	Performance Counter 0 Value Register
PP1_PERF_CNT_1_ENABLE	0x000000B0A0	32	rwNormal read/write	0x00000000	Performance Counter 1 Enable Register
PP1_PERF_CNT_1_SRC	0x000000B0A4	32	rwNormal read/write	0x00000000	Performance Counter 1 SRC Register
PP1_PERF_CNT_1_LIMIT	0x000000B0A8	32	rwNormal read/write	0x00000000	Performance Counter 1 Limit Register
PP1_PERF_CNT_1_VALUE	0x000000B0AC	32	rwNormal read/write	0x00000000	Performance Counter 1 Value Register
PP1_PERFMON_CONTR	0x000000B0B0	32	rwNormal read/write	0x00000000	Performance Monitor Control Register
PP1_PERFMON_BASE	0x000000B0B4	32	rwNormal read/write	0x00000000	Performance Monitor Base Address Register