PMCEID0 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PMCEID0 (SMMU500) Register Description

Register NamePMCEID0
Offset Address0x0000003E20
Absolute Address 0x00FD803E20 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x00030303
DescriptionPerformance Monitor Common Event Identification register 0 describes the event classes supported by the SMMU implementation.

PMCEID0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Event0x1217roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x1116roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x1015roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x0A 9roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x09 8roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x08 7roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x01 1roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x00 0roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details