RFSHCTL3 (DDRC) Register Description
| Register Name | RFSHCTL3 |
|---|---|
| Offset Address | 0x0000000060 |
| Absolute Address | 0x00FD070060 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Refresh Control Register 3 |
All register fields are dynamic - refresh related, unless described otherwise in the register field description. Refresh related dynamic registers can be written at any time during operation, but to update them the following must be done: * Change the refresh associated register as desired. * After the changed register is known stable, toggle the RFSHCTL3.refresh_update_level signal.
RFSHCTL3 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| refresh_mode | 6:4 | rwNormal read/write | 0x0 | Fine Granularity Refresh Mode (DDR4 only) - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not supported in this version of the DDRC. Note: Fine Granularity Refresh Mode is only supported in DDR4 mode. Note: This must be set up while the Controller is in reset or while the Controller is in self-refresh mode. Changing this during normal operation is not allowed. Programming Mode: Quasi-dynamic Group 2 |
| refresh_update_level | 1 | rwNormal read/write | 0x0 | Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value is automatically updated when exiting reset, so it does not need to be toggled initially. |
| dis_auto_refresh | 0 | rwNormal read/write | 0x0 | When 1, disable auto-refresh generated by the DDRC. When auto-refresh is disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh and reg_ddrc_rank1_refresh. When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to 0. This register field is changeable on the fly. |