INT_STAT_4 (GPIO) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INT_STAT_4 (GPIO) Register Description

Register NameINT_STAT_4
Offset Address0x0000000318
Absolute Address 0x00FF0A0318 (GPIO)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status (GPIO Bank4, EMIO Bank1)

This register operates in exactly the same manner as INT_STAT_0, except that it reflects bank4, which corresponds to EMIO[63:32].

INT_STAT_4 (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
INT_STATUS_431:0wtcReadable, write a 1 to clear0x0Interrupt status
Upon read:
0: no interrupt
1: interrupt event has occurred
Upon write:
0: no action
1: clear interrupt status bit
Each bit configures the corresponding pin within the 32-bit bank