RAM_RET_CNTRL (PMU_GLOBAL) Register Description
| Register Name | RAM_RET_CNTRL |
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| Offset Address | 0x0000000108 |
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| Absolute Address |
0x00FFD80108 (PMU_GLOBAL)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Memory Retention Requests. |
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Software may request to have the on-chip RAMs put into their memory retention state or be powered-down. For retention, software sets RAM_RET_CNTRL bit fields = 1. For power-down, set the bit = 0. When triggered (REQ_PWRDWN_TRIG), the RAM_RET_CNTRL bits select: 0: request is for power-down. 1: request is for RAM data retention. The power-down interrupt structure is used to mask and monitor the retention request. If any bit is set = 1, then the retention request is issued and not the power-down request. Example to power-down OCM bank 4 and put bank 3 into power retention state: Write 0 to [OCM_Bank4], write 1 to [OCM_Bank3] and write 0C00 to the REQ_PWRDWN_TRIG register.
RAM_RET_CNTRL (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:20 | roRead-only | 0x0 | reserved |
| OCM_Bank3 | 19 | rwNormal read/write | 0x0 | OCM Bank 3. |
| OCM_Bank2 | 18 | rwNormal read/write | 0x0 | OCM Bank 2. |
| OCM_Bank1 | 17 | rwNormal read/write | 0x0 | OCM Bank 1. |
| OCM_Bank0 | 16 | rwNormal read/write | 0x0 | OCM Bank 0. |
| TCM1B | 15 | rwNormal read/write | 0x0 | RPU core 1, TCM_B. |
| TCM1A | 14 | rwNormal read/write | 0x0 | RPU core 1, TCM_A. |
| TCM0B | 13 | rwNormal read/write | 0x0 | RPU core 0, TCM_B. |
| TCM0A | 12 | rwNormal read/write | 0x0 | RPU core 0, TCM_A. |
| Reserved | 11:9 | roRead-only | 0x0 | reserved |
| Reserved | 8 | roRead-only | 0x0 | reserved |
| L2_Bank0 | 7 | rwNormal read/write | 0x0 | APU L2 Cache. |
| Reserved | 6:0 | roRead-only | 0x0 | reserved |