reg_normalintrstsena (SDIO) Register Description
| Register Name | reg_normalintrstsena |
|---|---|
| Offset Address | 0x0000000034 |
| Absolute Address |
0x00FF160034 (SD0) 0x00FF170034 (SD1) |
| Width | 16 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Normal-type Interrupts Status Enables. |
Bit 0 through 7: 0: masked. 1: enabled.
reg_normalintrstsena (SDIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| normalintrsts_enableregbit15 | 15 | roRead-only | 0x0 | The HC shall control error Interrupts using the Error Interrupt Status Enable register. |
| normalintrsts_enableregbit14 | 14 | rwNormal read/write | 0x0 | Bit 14. |
| normalintrsts_enableregbit13 | 13 | rwNormal read/write | 0x0 | Bit 13. |
| normalintrsts_enableregbit12 | 12 | rwNormal read/write | 0x0 | This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. |
| normalintrsts_enableregbit11 | 11 | rwNormal read/write | 0x0 | If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts. |
| normalintrsts_enableregbit10 | 10 | rwNormal read/write | 0x0 | If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts. |
| normalintrsts_enableregbit9 | 9 | rwNormal read/write | 0x0 | If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts. |
| sdhcregset_cardintstsena | 8 | rwNormal read/write | 0x0 | If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interruptdetection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts. |
| sdhcregset_cardremstsena | 7 | rwNormal read/write | 0x0 | Bit 7. |
| sdhcregset_cardinsstsena | 6 | rwNormal read/write | 0x0 | Bit 6. |
| normalintrsts_enableregbit5 | 5 | rwNormal read/write | 0x0 | Bit 5. |
| normalintrsts_enableregbit4 | 4 | rwNormal read/write | 0x0 | Bit 4. |
| normalintrsts_enableregbit3 | 3 | rwNormal read/write | 0x0 | Bit 3. |
| normalintrsts_enableregbit2 | 2 | rwNormal read/write | 0x0 | Bit 2. |
| normalintrsts_enableregbit1 | 1 | rwNormal read/write | 0x0 | Bit 1. |
| normalintrsts_enableregbit0 | 0 | rwNormal read/write | 0x0 | Bit 0. |