SMMU_CB4_TCR2 (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

SMMU_CB4_TCR2 (SMMU500) Register Description

Register Name	SMMU_CB4_TCR2
Offset Address	0x0000014010
Absolute Address	0x00FD814010 (SMMU_GPV)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000060
Description	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.

SMMU_CB4_TCR2 (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
NSCFG1	30	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SEP	17:15	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSCFG0	14	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TBI1	6	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TBI0	5	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
AS	4	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PASize	2:0	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details