SMMU_CB10_TLBIALL (SMMU500) Register Description
| Register Name | SMMU_CB10_TLBIALL |
|---|---|
| Offset Address | 0x000001A618 |
| Absolute Address | 0x00FD81A618 (SMMU_GPV) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks. |
SMMU_CB10_TLBIALL (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| bits | 31:0 | woWrite-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |