Control (UART) Register Description
| Register Name | Control |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FF000000 (UART0) 0x00FF010000 (UART1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000128 |
| Description | UART Control Register |
The UART Control register is used to enable and reset the transmitter and receiver blocks. It also controls the receiver timeout and the transmission of breaks.
Control (UART) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:9 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| STPBRK | 8 | rwNormal read/write | 0x1 | Stop transmitter break: 0: no effect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. |
| STTBRK | 7 | rwNormal read/write | 0x0 | Start transmitter break: 0: no effect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. |
| RSTTO | 6 | rwNormal read/write | 0x0 | Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. |
| TXDIS | 5 | rwNormal read/write | 0x1 | Transmit disable: 0: enable transmitter 1: disable transmitter |
| TXEN | 4 | rwNormal read/write | 0x0 | Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. |
| RXDIS | 3 | rwNormal read/write | 0x1 | Receive disable: 0: enable 1: disable, regardless of the value of RXEN |
| RXEN | 2 | rwNormal read/write | 0x0 | Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. |
| TXRES | 1 | rwNormal read/write | 0x0 | Software reset for Tx data path: 0: no effect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. |
| RXRES | 0 | rwNormal read/write | 0x0 | Software reset for Rx data path: 0: no effect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. |