PMU_GLOBAL Module

PMU_GLOBAL Module - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

PMU_GLOBAL Module Description

Module Name	PMU_GLOBAL Module
Modules of this Type	PMU_GLOBAL
Base Addresses	0x00FFD80000 (PMU_GLOBAL)
Description	PMU Global Control

PMU_GLOBAL Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
GLOBAL_CNTRL	0x0000000000	32	mixedMixed types. See bit-field details.	0x00008800	PMU control and status register.
PS_CNTRL	0x0000000004	32	mixedMixed types. See bit-field details.	0x00000000	PL Program Initiation Control.
APU_PWR_STATUS_INIT	0x0000000008	32	mixedMixed types. See bit-field details.	0x00000000	APU Power Initialization Status.
ADDR_ERROR_STATUS	0x0000000010	32	mixedMixed types. See bit-field details.	0x00000000	Register Address Error; Interrupt Status and Clear.
ADDR_ERROR_INT_MASK	0x0000000014	32	roRead-only	0x00000001	Register Address Error; Interrupt Mask.
ADDR_ERROR_INT_EN	0x0000000018	32	woWrite-only	0x00000000	Register Address Error; Interrupt Enable.
ADDR_ERROR_INT_DIS	0x000000001C	32	woWrite-only	0x00000000	Register Address Error; Interrupt Disable.
GLOBAL_GEN_STORAGE0	0x0000000030	32	rwNormal read/write	0x00000000	Global Storage, Reg 0.
GLOBAL_GEN_STORAGE1	0x0000000034	32	rwNormal read/write	0x00000000	Global Storage, Reg 1.
GLOBAL_GEN_STORAGE2	0x0000000038	32	rwNormal read/write	0x00000000	Global Storage, Reg 2.
GLOBAL_GEN_STORAGE3	0x000000003C	32	rwNormal read/write	0x00000000	Global Storage, Reg 3.
GLOBAL_GEN_STORAGE4	0x0000000040	32	rwNormal read/write	0x00000000	Global Storage, Reg 4.
GLOBAL_GEN_STORAGE5	0x0000000044	32	rwNormal read/write	0x00000000	Global Storage, Reg 5.
GLOBAL_GEN_STORAGE6	0x0000000048	32	rwNormal read/write	0x00000000	Global Storage, Reg 6.
PERS_GLOB_GEN_STORAGE0	0x0000000050	32	rwNormal read/write	0x00000000	Persistent Global Storage, Reg 0.
PERS_GLOB_GEN_STORAGE1	0x0000000054	32	rwNormal read/write	0x00000000	Persistent Global Storage, Reg 1.
PERS_GLOB_GEN_STORAGE2	0x0000000058	32	rwNormal read/write	0x00000000	Persistent Global Storage, Reg 2.
PERS_GLOB_GEN_STORAGE3	0x000000005C	32	rwNormal read/write	0x00000000	Persistent Global Storage, Reg 3.
PERS_GLOB_GEN_STORAGE4	0x0000000060	32	rwNormal read/write	0x00000000	Persistent Global Storage, Reg 4.
PERS_GLOB_GEN_STORAGE5	0x0000000064	32	rwNormal read/write	0x00000000	Persistent Global Storage, Reg 5.
PERS_GLOB_GEN_STORAGE6	0x0000000068	32	rwNormal read/write	0x00000000	Persistent Global Storage, Reg 6.
PERS_GLOB_GEN_STORAGE7	0x000000006C	32	rwNormal read/write	0x00000000	Persistent Global Storage, Reg 7.
DDR_CNTRL	0x0000000070	1	rwNormal read/write	0x00000000	DDR Output Signal Latch Control.
PWR_STATE	0x0000000100	32	roRead-only	0x00FFFCBF	Power State Status; PS Islands, PL Internal and FPD.
AUX_PWR_STATE	0x0000000104	32	roRead-only	0x000FF080	Memory Retention and RPU Emulation State.
RAM_RET_CNTRL	0x0000000108	32	mixedMixed types. See bit-field details.	0x00000000	Memory Retention Requests.
PWR_SUPPLY_STATUS	0x000000010C	32	roRead-only	0x00000004	PS Power Supply Status.
REQ_PWRUP_STATUS	0x0000000110	32	mixedMixed types. See bit-field details.	0x00000000	Power-up Request; Interrupt Status and Clear.
REQ_PWRUP_INT_MASK	0x0000000114	32	roRead-only	0x00FFF4BF	Power-up Request; Interrupt Mask.
REQ_PWRUP_INT_EN	0x0000000118	32	woWrite-only	0x00000000	Power-up Request; Interrupt Enable.
REQ_PWRUP_INT_DIS	0x000000011C	32	woWrite-only	0x00000000	Power-up Request; Interrupt Disable.
REQ_PWRUP_TRIG	0x0000000120	32	woWrite-only	0x00000000	Power-up Request; Interrupt Trigger.
REQ_PWRDWN_STATUS	0x0000000210	32	mixedMixed types. See bit-field details.	0x00000000	Power-down or RAM Retention Request; Interrupt Status and Clear.
REQ_PWRDWN_INT_MASK	0x0000000214	32	roRead-only	0x00FFF4BF	Power-down or RAM Retention Request; Interrupt Mask.
REQ_PWRDWN_INT_EN	0x0000000218	32	woWrite-only	0x00000000	Power-down or RAM Retention Request; Interrupt Enable.
REQ_PWRDWN_INT_DIS	0x000000021C	32	woWrite-only	0x00000000	Power-down or RAM Retention Request; Interrupt Disable.
REQ_PWRDWN_TRIG	0x0000000220	32	woWrite-only	0x00000000	Power-down or RAM Retention Request; Interrupt Trigger.
REQ_ISO_STATUS	0x0000000310	32	mixedMixed types. See bit-field details.	0x00000000	Isolation Request; Interrupt Status and Clear.
REQ_ISO_INT_MASK	0x0000000314	32	roRead-only	0x00000017	Isolation Request; Interrupt Mask.
REQ_ISO_INT_EN	0x0000000318	32	woWrite-only	0x00000000	Isolation Request; Interrupt Enable.
REQ_ISO_INT_DIS	0x000000031C	32	woWrite-only	0x00000000	Isolation Request; Interrupt Disable.
REQ_ISO_TRIG	0x0000000320	32	woWrite-only	0x00000000	Isolation Request; Interrupt Trigger.
REQ_SWRST_STATUS	0x0000000410	32	mixedMixed types. See bit-field details.	0x00000000	Reset Request; Interrupt Status and Clear.
REQ_SWRST_INT_MASK	0x0000000414	32	roRead-only	0xFBF717DF	Reset Request; Interrupt Mask. Check the REQ_SWRST_STATUS register bits for more information.
REQ_SWRST_INT_EN	0x0000000418	32	woWrite-only	0x00000000	Reset Request; Interrupt Enable. Check the REQ_SWRST_STATUS register bits for more information.
REQ_SWRST_INT_DIS	0x000000041C	32	woWrite-only	0x00000000	Reset Request; Interrupt Disable. Check the REQ_SWRST_STATUS register bits for more information.
REQ_SWRST_TRIG	0x0000000420	32	woWrite-only	0x00000000	Reset Request; Interrupt Trigger. Check the REQ_SWRST_STATUS register bits for more information.
CSU_BR_ERROR	0x0000000528	32	mixedMixed types. See bit-field details.	0x00000000	BootROM Error detection and code.
MB_FAULT_STATUS	0x000000052C	32	roRead-only	0x00000000	PMU Fault Status; Lockstep, Fatal, Selfcheck, Sleep Instruction.
ERROR_STATUS_1	0x0000000530	32	mixedMixed types. See bit-field details.	0x00000000	System Errors; Interrupt Clear and Status, Reg 1.
ERROR_INT_MASK_1	0x0000000534	32	roRead-only	0x0FFF32FF	System Errors to PMU; Interrupt Mask, Reg 1.
ERROR_INT_EN_1	0x0000000538	32	woWrite-only	0x00000000	System Errors to PMU; Interrupt Enable, Reg 1.
ERROR_INT_DIS_1	0x000000053C	32	woWrite-only	0x00000000	System Errors to PMU; Interrupt Disable, Reg 1.
ERROR_STATUS_2	0x0000000540	32	mixedMixed types. See bit-field details.	0x00000000	System Errors; Interrupt Clear and Status, Reg 2.
ERROR_INT_MASK_2	0x0000000544	32	roRead-only	0x073F1F3F	System Errors to PMU; Interrupt Mask, Reg 2.
ERROR_INT_EN_2	0x0000000548	32	woWrite-only	0x00000000	System Errors to PMU; Interrupt Enable, Reg 2.
ERROR_INT_DIS_2	0x000000054C	32	woWrite-only	0x00000000	System Errors to PMU; Interrupt Disable, Reg 2.
ERROR_POR_MASK_1	0x0000000550	32	roRead-only	0x0FFF32FF	System Errors to POR; Interrupt Mask, Reg 1.
ERROR_POR_EN_1	0x0000000554	32	woWrite-only	0x00000000	System Errors to POR; Interrupt Enable, Reg 1.
ERROR_POR_DIS_1	0x0000000558	32	woWrite-only	0x00000000	System Errors to POR; Interrupt Disable, Reg 1.
ERROR_POR_MASK_2	0x000000055C	32	roRead-only	0x073F1F3F	System Error to POR; Interrupt Mask, Reg 2.
ERROR_POR_EN_2	0x0000000560	32	woWrite-only	0x00000000	System Errors to POR; Interrupt Enable, Reg 2.
ERROR_POR_DIS_2	0x0000000564	32	woWrite-only	0x00000000	System Errors to POR; Interrupt Disable, Reg 2.
ERROR_SRST_MASK_1	0x0000000568	32	roRead-only	0x0FFF32FF	System Errors to Reset; Interrupt Mask, Reg 1.
ERROR_SRST_EN_1	0x000000056C	32	woWrite-only	0x00000000	System Errors to Reset; Interrupt Enable, Reg 1.
ERROR_SRST_DIS_1	0x0000000570	32	woWrite-only	0x00000000	System Errors to Reset; Interrupt Disable, Reg 1.
ERROR_SRST_MASK_2	0x0000000574	32	roRead-only	0x073F1F3F	System Errors to Reset; Interrupt Mask, Reg 2.
ERROR_SRST_EN_2	0x0000000578	32	woWrite-only	0x00000000	System Errors to Reset; Interrupt Enable, Reg 2.
ERROR_SRST_DIS_2	0x000000057C	32	woWrite-only	0x00000000	System Errors to Reset; Interrupt Disable, Reg 2.
ERROR_SIG_MASK_1	0x0000000580	32	roRead-only	0x000000C3	System Errors to PL; Interrupt Mask, Reg 1.
ERROR_SIG_EN_1	0x0000000584	32	woWrite-only	0x00000000	System Errors to PL; Interrupt Enable, Reg 1.
ERROR_SIG_DIS_1	0x0000000588	32	woWrite-only	0x00000000	System Errors to PL; Interrupt Disable, Reg 1.
ERROR_SIG_MASK_2	0x000000058C	32	roRead-only	0x00001F00	System Errors to PL; Interrupt Mask, Reg 2.
ERROR_SIG_EN_2	0x0000000590	32	woWrite-only	0x00000000	System Errors to PL; Interrupt Enable, Reg 2.
ERROR_SIG_DIS_2	0x0000000594	32	woWrite-only	0x00000000	System Errors to PL; Interrupt Disable, Reg 2.
ERROR_EN_1	0x00000005A0	32	rwNormal read/write	0x00000000	System Error Enables, Reg 1.
ERROR_EN_2	0x00000005A4	32	rwNormal read/write	0x073E0000	System Error Enables, Reg 2.
AIB_CNTRL	0x0000000600	32	woWrite-only	0x00000000	PS-PL AXI Bus Logic Isolation Requests.
AIB_STATUS	0x0000000604	32	roRead-only	0x00000000	PS-PL AXI Bus Logic Isolation Status.
GLOBAL_RESET	0x0000000608	32	mixedMixed types. See bit-field details.	0x00000000	GLOBAL_RESET
ROM_VALIDATION_STATUS	0x0000000610	32	roRead-only	0x00000000	PMU ROM validation engine status.
ROM_VALIDATION_DIGEST_0	0x0000000614	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 0.
ROM_VALIDATION_DIGEST_1	0x0000000618	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 1.
ROM_VALIDATION_DIGEST_2	0x000000061C	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 2.
ROM_VALIDATION_DIGEST_3	0x0000000620	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 3.
ROM_VALIDATION_DIGEST_4	0x0000000624	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 4.
ROM_VALIDATION_DIGEST_5	0x0000000628	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 5.
ROM_VALIDATION_DIGEST_6	0x000000062C	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 6.
ROM_VALIDATION_DIGEST_7	0x0000000630	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 7.
ROM_VALIDATION_DIGEST_8	0x0000000634	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 8.
ROM_VALIDATION_DIGEST_9	0x0000000638	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 9.
ROM_VALIDATION_DIGEST_10	0x000000063C	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 10.
ROM_VALIDATION_DIGEST_11	0x0000000640	32	roRead-only	0xFFFFFFFF	PMU ROM Validation SHA value, Word 11.
SAFETY_GATE	0x0000000650	32	mixedMixed types. See bit-field details.	0x00000007	Safety gates disable hardware functions.
MBIST_RST	0x0000000700	32	rwNormal read/write	0x00000000	On-demand MBIST Controller Reset, Trigger 0.
MBIST_PG_EN	0x0000000704	32	rwNormal read/write	0x00000000	On-demand MBIST, Trigger 1.
MBIST_SETUP	0x0000000708	32	rwNormal read/write	0x00000000	On-demand MBIST, Trigger 2.
MBIST_DONE	0x0000000710	32	roRead-only	0x00000000	MBIST Done Indicator.
MBIST_GOOD	0x0000000714	32	roRead-only	0x00000000	MBIST Result Status.
SAFETY_CHK	0x0000000800	32	rwNormal read/write	0x00000000	Test ability to access this register set. Can be used at any time by any master with accessibility.