SMMU_CB5_TLBIVAA_low (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB5_TLBIVAA_low (SMMU500) Register Description

Register NameSMMU_CB5_TLBIVAA_low
Offset Address0x0000015608
Absolute Address 0x00FD815608 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInvalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.

SMMU_CB5_TLBIVAA_low (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Address31:0woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details