OCM_ERR_CTRL (OCM) Register Description
| Register Name | OCM_ERR_CTRL |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FF960000 (OCM) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x0000000F |
| Description | Enable/Disable a error response |
By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur.
OCM_ERR_CTRL (OCM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | razRead as zero | 0x0 | |
| UE_RES | 3 | rwNormal read/write | 0x1 | ECC has detected double bit error (uncorrectable error ), the resulting slave eror will be: 0: slverr = 1b0 1: slverr = 1b1 There is also a maskable interrupt , "ECC_UE_INT" that could be asserted, independent of what option is selected here. |
| PWR_ERR_RES | 2 | rwNormal read/write | 0x1 | Software generates access to power down bank, the resulting decode eror will be: 0: decerr = 1b0 1: decerr = 1b1 There is also a maskable interrupt , "PWRDN_BNK_INT" that could be asserted, independent of what option is selected here. |
| PZ_ERR_RES | 1 | rwNormal read/write | 0x1 | XMPU security check fails, XMPU asserts poison signal on read and write channel.When XMPU asserts poison signal, the resulting decode error will be: 0: decerr = 1b0 1: decerr = 1b1 There is also a maskable interrupt , "INV_OCM_INT" that could be asserted, independent of what option is selected here. |
| APB_ERR_RES | 0 | rwNormal read/write | 0x1 | When an APB (register) access occurs to an unimplemented space (there is no register at that location), the resulting pslverr will be: 0: pslverr = 1b0 1: pslverr = 1b1 There is also a maskable interrupt , "INV_APB_INT" that could be asserted, independent of what option is selected here. |