MASK_DATA_0_MSW (GPIO) Register Description
| Register Name | MASK_DATA_0_MSW |
|---|
| Offset Address | 0x0000000004 |
|---|
| Absolute Address |
0x00FF0A0004 (GPIO)
|
|---|
| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | Maskable Output Data (GPIO Bank0, MIO, Upper 10bits) |
|---|
This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 10bits of bank0, which corresponds to MIO[25:16].
MASK_DATA_0_MSW (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
| MASK_0_MSW | 25:16 | woWrite-only | 0x0 | Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW] |
| Reserved | 15:10 | razRead as zero | 0x0 | Not used, read back as zero |
| DATA_0_MSW | 9:0 | rwNormal read/write | 0 | Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW] |