PMU_LOCAL Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

PMU_LOCAL Module Description

Module Name	PMU_LOCAL Module
Modules of this Type	PMU_LOCAL
Base Addresses	0x00FFD60000 (PMU_LOCAL)
Description	PMU MicroBlaze Processor Local Control

PMU_LOCAL Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
ACPU0_PWR_CNTRL	0x0000000000	32	mixedMixed types. See bit-field details.	0x0000000F	APU Core 0 Power and Isolation Control. Reset by POR only.
ACPU0_PWR_STATUS	0x0000000004	32	roRead-only	0x0000000F	APU Core 0 Power Status. Reset by POR only.
ACPU1_PWR_CNTRL	0x0000000010	32	mixedMixed types. See bit-field details.	0x0000000F	APU Core 1 Power and Isolation Control. Reset by POR only.
ACPU1_PWR_STATUS	0x0000000014	32	roRead-only	0x0000000F	APU Core 1 Power Status. Reset by POR only.
ACPU2_PWR_CNTRL	0x0000000020	32	mixedMixed types. See bit-field details.	0x0000000F	APU Core 2 Power and Isolation Control. Reset by POR only.
ACPU2_PWR_STATUS	0x0000000024	32	roRead-only	0x0000000F	APU Core 2 Power Status. Reset by POR only.
ACPU3_PWR_CNTRL	0x0000000030	32	mixedMixed types. See bit-field details.	0x0000000F	APU Core 3 Power and Isolation Control. Reset by POR only.
ACPU3_PWR_STATUS	0x0000000034	32	roRead-only	0x0000000F	APU Core 3 Power Status. Reset by POR only.
PP0_PWR_CNTRL	0x0000000040	32	mixedMixed types. See bit-field details.	0x0000000F	GPU PP0 Power and Isolation Control. Reset by POR only.
PP0_PWR_STATUS	0x0000000044	32	roRead-only	0x0000000F	GPU PP0 Power Status. Reset by POR only.
PP1_PWR_CNTRL	0x0000000048	32	mixedMixed types. See bit-field details.	0x0000000F	GPU PP1 Power and Isolation Control. Reset by POR only.
PP1_PWR_STATUS	0x000000004C	32	roRead-only	0x0000000F	GPU PP1 Power Status. Reset by POR only.
USB0_PWR_CNTRL	0x0000000060	32	mixedMixed types. See bit-field details.	0x0000000F	USB 0 Power and Isolation Control. Reset by POR only.
USB0_PWR_STATUS	0x0000000064	32	roRead-only	0x0000000F	USB0 Power Status. Reset by POR only.
USB1_PWR_CNTRL	0x0000000070	32	mixedMixed types. See bit-field details.	0x0000000F	USB 1 Power and Isolation Control. Reset by POR only.
USB1_PWR_STATUS	0x0000000074	32	roRead-only	0x0000000F	USB1 Power Status. Reset by POR only.
RPU_PWR_CNTRL	0x0000000080	32	mixedMixed types. See bit-field details.	0x0000000F	RPU MPCore Power and Isolation Control. Reset by POR only.
RPU_PWR_STATUS	0x0000000084	32	roRead-only	0x0000000F	RPU MPCore Power Status. Reset by POR only.
L2_PWR_CNTRL	0x00000000B0	32	mixedMixed types. See bit-field details.	0x00000001	L2 Cache Power Control. Reset by POR only.
L2_RET_CNTRL	0x00000000B4	32	mixedMixed types. See bit-field details.	0x00000000	L2 Cache Memory Retention Controls. Reset only by POR.
L2_CE_CNTRL	0x00000000B8	32	mixedMixed types. See bit-field details.	0x00000001	L2 Cache Memory Chip Enables. Reset only by POR.
L2_PWR_STATUS	0x00000000BC	32	roRead-only	0x00000001	L2 Cache Memory Power Status.
OCM_PWR_CNTRL	0x00000000C0	32	mixedMixed types. See bit-field details.	0x01010101	OCM Memory Power Control. Reset only by POR.
OCM_RET_CNTRL	0x00000000C4	32	mixedMixed types. See bit-field details.	0x00000000	OCM Memory Retention Controls. Reset only by POR.
OCM_CE_CNTRL	0x00000000C8	32	mixedMixed types. See bit-field details.	0x0000000F	OCM Memory Chip Enables. Reset only by POR.
OCM_PWR_STATUS	0x00000000CC	32	roRead-only	0x01010101	OCM Memory Power Status.
TCM_PWR_CNTRL	0x00000000D0	32	mixedMixed types. See bit-field details.	0x01010101	RPU TCM Memory Power Control. Reset by POR only.
TCM_RET_CNTRL	0x00000000D4	32	mixedMixed types. See bit-field details.	0x00000000	RPU TCM Retention Controls.
TCM_CE_CNTRL	0x00000000D8	32	mixedMixed types. See bit-field details.	0x0000000F	RPU TCM Chip Enables.
TCM_PWR_STATUS	0x00000000DC	32	roRead-only	0x01010101	RPU TCM Power Switch Status.
DOMAIN_ISO_CNTRL	0x00000000F0	32	mixedMixed types. See bit-field details.	0x00000028	Isolation Wall Enable Control. Reset only by POR.
LOC_PWR_STATE	0x0000000100	32	mixedMixed types. See bit-field details.	0x003FFCBF	Power Island Status.
LOC_AUX_PWR_STATE	0x0000000104	32	mixedMixed types. See bit-field details.	0x000FF080	RAM Retention and Processor Emulation States.
LOCAL_RESET	0x0000000200	32	mixedMixed types. See bit-field details.	0x00000001	CSU Reset Control.
LOCAL_CNTRL	0x0000000204	32	mixedMixed types. See bit-field details.	0x00000000	PMU Controls.
GPO1_READ	0x0000000214	32	roRead-only	0x00000000	PMU GPO1 Output Register State.
GPO2_READ	0x0000000218	32	roRead-only	0x00000000	PMU GPO2 Output Register State.
GPO3_READ	0x000000021C	32	roRead-only	0x00000000	PMU GPO3 Output Register State.
GPI1_ENABLE	0x0000000224	32	mixedMixed types. See bit-field details.	0x00000000	Enable Events on PMU GPI1 Input Register.
GPI2_ENABLE	0x0000000228	32	mixedMixed types. See bit-field details.	0x00000000	Enable Events on PMU GPI2 Input Register.
GPI3_ENABLE	0x000000022C	32	rwNormal read/write	0x00000000	Enable Events on PMU GPI3 Input Register.
BOOT_PWR_SUPPLY_CACHE	0x0000000300	32	rwNormal read/write	0x00000000	Power Supply Status and General Purpose Read-Write.
BOOT_STAGE	0x0000000304	32	rwNormal read/write	0x00000000	PMU Boot Stage and General Purpose Read-Write.
LAST_UNDEFINED_SERV	0x0000000308	32	rwNormal read/write	0x00000000	PMU ROM code: ID Value of ROM Undefiend Service Request.
LAST_SERV	0x000000030C	32	rwNormal read/write	0x00000000	PMU ROM code: ID Value of ROM Service Request.
PERS_LOC_GEN_STORAGE0	0x0000000310	32	rwNormal read/write	0x00000000	Persistent Local General Storage. Reset by POR only.
PERS_LOC_GEN_STORAGE1	0x0000000314	32	rwNormal read/write	0x00000000	Persistent Local General Storage. Reset by POR only.
PERS_LOC_GEN_STORAGE2	0x0000000318	32	rwNormal read/write	0x00000000	Persistent Local General Storage. Reset by POR only.
PERS_LOC_GEN_STORAGE3	0x000000031C	32	rwNormal read/write	0x00000000	Persistent Local General Storage. Reset by POR only.
ADDR_ERROR_STATUS	0x0000000320	1	wtcReadable, write a 1 to clear	0x00000000	Address Error Decode Interrupt Status.
ADDR_ERROR_INT_MASK	0x0000000324	1	roRead-only	0x00000001	Address Error Decode Interrupt Mask.
ADDR_ERROR_INT_EN	0x0000000328	1	woWrite-only	0x00000000	Address Error Decode Interrupt Enable.
ADDR_ERROR_INT_DIS	0x000000032C	1	woWrite-only	0x00000000	Address Error Decode Interrupt Disable.
MBISR_CNTRL	0x0000000330	32	mixedMixed types. See bit-field details.	0x00000000	Controls the MBISR engines in the FPD.
MBISR_STATUS	0x0000000334	32	roRead-only	0x00000000	Completion Status of MBISR engines.
PMU_PB_ERR	0x0000000338	32	rwNormal read/write	0x00000000	Errors Detected During PMU Pre-Boot.
PMU_SERV_ERR	0x000000033C	32	mixedMixed types. See bit-field details.	0x00000000	Errors Detected During PMU ROM Pre-Boot. Reset by POR only.
PWR_ACK_ERR_LPD	0x0000000340	32	rwNormal read/write	0x00000000	PRDY Status Error for Power Islands in LPD. Reset only by POR.
PWR_ACK_ERR_FPD	0x0000000344	32	rwNormal read/write	0x00000000	PRDY Status Error for Power Islands in FPD. Reset only by POR.
SERV_LOGCLR_ERR	0x0000000348	32	rwNormal read/write	0x00000000	Logic Clear Services Log Error Status. Reset only by POR.
LOGCLR_TRIG	0x0000000350	32	woWrite-only	0x00000000	Request to start the Logic Clear Engines.
LOGCLR_ACK	0x0000000354	32	roRead-only	0x00000000	This register provides the Acknowledge from the Logic Clear engines after they are run. (1 = Zeroization is Completed)
APU_WFI_STATUS	0x0000000360	32	roRead-only	0x00000000	This register provides the status of the WFI state for the ACPU3-ACPU0 and the L2 Cache.
MBIST_RST	0x000000036C	2	rwNormal read/write	0x00000000	This register is used to control the Reset to the MBIST Memory Controllers for PMU and CSU
MBIST_PG_EN	0x0000000370	2	rwNormal read/write	0x00000000	This register is used to control the PG_EN signal to the MBIST Memory Controllers for PMU and CSU
MBIST_SETUP	0x0000000374	2	rwNormal read/write	0x00000000	This register is used to control the SETUP_1 signal to the MBIST Memory Controllers for PMU and CSU
MBIST_DONE	0x0000000378	2	roRead-only	0x00000000	This register is used to read the DONE status of the MBIST Memory Controllers for PMU and CSU
MBIST_GOOD	0x000000037C	2	roRead-only	0x00000000	This register is used to read the GO status of the MBIST Memory Controllers for PMU and CSU