PP0_CTRL_MGMT (GPU) Register Description
| Register Name | PP0_CTRL_MGMT |
|---|---|
| Offset Address | 0x000000900C |
| Absolute Address | 0x00FD4B900C (GPU) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Control Management Register |
PP0_CTRL_MGMT (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| _ | 31:9 | woWrite-only | 0x0 | Reserved, write as zero, read undefined. |
| CLK_OVERRIDE | 8 | woWrite-only | 0x0 | Disable block level clock gates. Writing a 1 to this bit overrides all the architectural clock gates in the design, so all clocks are always active. The status of the clock override is shown as the CLK_OVERRIDE bit in the STATUS Register. The only way to disable the clock override is by performing a pixel processor reset. |
| SOFT_RESET | 7 | woWrite-only | 0x0 | Writing to this bit resets the pixel processor after all outstanding bus-transfers have completed. Use the RESET_COMPLETED interrupt bit to discover when the reset has actually completed. |
| START_RENDERING | 6 | woWrite-only | 0x0 | Writing to this bit initiates rendering. Do not write this value during rendering. |
| FORCE_RESET | 5 | woWrite-only | 0x0 | Writing to this bit resets the pixel processor, so that it can be brought out of a hang in a reasonably clean manner. If FORCE_RESET is asserted while there is a bus transaction in progress the AXI interconnect might operate at reduced efficiency or lockup. To ensure a safe reset: 1. Write 1 to STOP_BUS. 2. Wait until all transactions have completed. The BUS_STOP interrupt is asserted when the bus is idle. 3. Write 1 to FORCE_RESET. The use of FORCE_RESET must be deprecated, unless you require backwards compatibility with Mali-200. |
| FORCE_HANG | 4 | woWrite-only | 0x0 | Writing to this bit causes the pixel processor to hang. Only useful for debugging. |
| FLUSH_CACHES | 3 | woWrite-only | 0x0 | Writing to this bit causes all the vertex, RSW and texture caches to be flushed immediately. This must be done only when the renderer is idle, otherwise the hardware cannot guarantee that caches become clean or that renderer glitches do not occur. The pixel processor must have an active clock for the flush to have an effect. The pixel processor might have the clock shut off when idle to conserve power, depending on the processor integration. This means that the FLUSH_CACHES command must be issued in of the following states of operation: 1. At the beginning of a frame, after the APB registers have been written to, but before the START_RENDERING command has been issued. 2. At the end of a frame, after the interrupt has been received but before the interrupt signal has been masked or acknowledged. If neither is possible, you can use a FORCE_RESET command to flush the caches. FLUSH_CACHES is performed implicitly every time the pixel processor starts rendering, so explicitly using this bit is rarely required. |
| END_AFTER_TILE | 2 | woWrite-only | 0x0 | Writing to this bit causes the renderer to treat a BEGIN-NEW-TILE command, that is, Cmd 14, as an End-Of-List command, that is Cmd 15. This action finalizes the rendering of the current tile, leaving the framebuffer incomplete in most situations, except when the current tile is the last tile of the frame. Rendering of the rest of the frame can be initiated by writing the CURRENT_REND_LIST_ADDR value to the REND_LIST_ADDR Register and issuing the START_RENDERING command. |
| START_BUS | 1 | woWrite-only | 0x0 | Writing to this bit reactivates the bus interface after it has been stopped by a STOP_BUS command or a WRITE_BOUNDARY_LIMIT event. The effect of issuing a START_BUS and a STOP_BUS command at the same time is not defined. |
| STOP_BUS | 0 | woWrite-only | 0x0 | Writing to this bit causes the bus interface to hold back future transactions on the bus. Any current bus transactions are completed before the interface is stopped. The bus can be restarted by issuing a START_BUS command. The effect of issuing a START_BUS and a STOP_BUS command at the same time is not defined. |