DQMAP0 (DDRC) Register Description
| Register Name | DQMAP0 |
|---|
| Offset Address | 0x0000000280 |
|---|
| Absolute Address |
0x00FD070280 (DDRC)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | DQ Map Register 0 |
|---|
This register is static. Static registers can only be written when the controller is in reset.
DQMAP0 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| dq_nibble_map_12_15 | 31:24 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [12-15] |
| dq_nibble_map_8_11 | 23:16 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [8-11] |
| dq_nibble_map_4_7 | 15:8 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [4-7] |
| dq_nibble_map_0_3 | 7:0 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [0-3] |