GBUSERRADDRHI (USB3_XHCI) Register Description
| Register Name | GBUSERRADDRHI |
|---|---|
| Offset Address | 0x000000C134 |
| Absolute Address |
0x00FE20C134 (USB3_0_XHCI) 0x00FE30C134 (USB3_1_XHCI) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Gobal SoC Bus Error Address Register - High This is an alternate register for the GBUSERRADDR register. |
GBUSERRADDRHI (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| BUSERRADDR | 31:0 | roRead-only | 0x0 | Bus Address - High (BusAddrHi) This register contains the higher 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the core. Note: Only supported in AHB and AXI configurations. |